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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

8305AGILF

RENESAS · Clock Buffers, Drivers · TSSOP-16

8305AGILF from RENESAS, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Power supply ground.
2	OE	input	Output enable pin with internal pull-up: when LOW the outputs are in the active state, and when HIGH the outputs are in the high impedance state, with LVCMOS/LVTTL interface levels.
3	VDD	power_in	Core power supply.
4	CLK_EN	input	Synchronized clock enable with internal pull-up: when HIGH the clock outputs follow the clock input, and when LOW the clock outputs are forced LOW, with LVCMOS/LVTTL interface levels.
5	CLK	input	Non-inverting differential clock input with internal pull-down, used when CLK_SEL is HIGH.
6	nCLK	input	Inverting differential clock input with internal pull-up and pull-down, defaulting to VDD/2 when left floating.
7	CLK_SEL	input	Clock select input with internal pull-up: when HIGH it selects the CLK/nCLK differential input, and when LOW it selects the LVCMOS_CLK input, with LVCMOS/LVTTL interface levels.
8	LVCMOS_CLK	input	Single-ended LVCMOS/LVTTL clock input with internal pull-down, used when CLK_SEL is LOW.
9	GND	power_in	Power supply ground.
10	Q3	output	LVCMOS/LVTTL clock output 3.
11	VDDO	power_in	Output supply voltage for Q0 to Q3.
12	Q2	output	LVCMOS/LVTTL clock output 2.
13	GND	power_in	Power supply ground.
14	Q1	output	LVCMOS/LVTTL clock output 1.
15	VDDO	power_in	Output supply voltage for Q0 to Q3.
16	Q0	output	LVCMOS/LVTTL clock output 0.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	TSSOP-16
Category	Clock and Timing
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input high voltage	VIH	2			V	OE, CLK_SEL, CLK_EN	4
Input high current	IIH			5	µA	OE, CLK_SEL, CLK_EN, VDD = 3.465V	4
Maximum output frequency	fMAX			350	MHz		1
Output skew	tsk(o)			40	ps		5
Supply voltage	VDD			4.6	V		4
Inputs voltage	VI	-0.5			V	Maximum is VDD + 0.5V	4
Outputs voltage	VO	-0.5			V	Maximum is VDDO + 0.5V	4
Storage temperature	TSTG	-65		150	°C		4
Ambient operating temperature	TA	-40		85	°C		1
Package thermal impedance, junction to ambient	θJA		89		°C/W	0 lfpm, multi-layer PCB	12

CAD (KiCad official)

Symbol: 8305AGILF
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: 8305agilf-etched.step / 8305agilf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 8305agilf.step / 8305agilf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (17 pp, sha256 d908743cb8e9fa41, retrieved 2026-10-28, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF