74LVC594APW

{
  "slug": "74lvc594apw",
  "version": "0.1.0",
  "type": "component",
  "description": "Nexperia Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "74lvc594apw",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
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    "README.md",
    "74lvc594apw.kicad_sym",
    "74lvc594apw.kicad_mod",
    "74lvc594apw.glb",
    "74lvc594apw.step",
    "74lvc594apw.lbr",
    "docs/hero.png",
    "docs/74lvc594apw-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "74lvc594apw-hero.glb",
    "74lvc594apw-hero.overlay.json",
    "74lvc594apw-etched.glb"
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  "component": {
    "mpn": "74LVC594APW",
    "manufacturer": "Nexperia",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shift Registers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908360779370496",
    "parts": {
      "symbol": "74lvc594apw.kicad_sym",
      "footprint": "74lvc594apw.kicad_mod",
      "model_3d": "74lvc594apw-hero.glb",
      "model_3d_plain": "74lvc594apw-etched.glb",
      "model_3d_step": "74lvc594apw-etched.step",
      "model_3d_step_plain": "74lvc594apw.step",
      "lbr": "74lvc594apw.lbr"
    },
    "distributor_links": {
      "lcsc": "C548830",
      "mouser": "771-74LVC594APW"
    },
    "distributor_check": {
      "checked_at": "2026-10-19T04:59:10Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": "771-74LVC594APW",
        "status": "found",
        "lifecycle": "End of Life"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "Q1",
        "type": "output",
        "description": "Parallel data output from storage register stage 1; output voltage is 0 V to VCC in the HIGH or LOW state."
      },
      {
        "number": "2",
        "name": "Q2",
        "type": "output",
        "description": "Parallel data output from storage register stage 2; output voltage is 0 V to VCC in the HIGH or LOW state."
      },
      {
        "number": "3",
        "name": "Q3",
        "type": "output",
        "description": "Parallel data output from storage register stage 3; output voltage is 0 V to VCC in the HIGH or LOW state."
      },
      {
        "number": "4",
        "name": "Q4",
        "type": "output",
        "description": "Parallel data output from storage register stage 4; output voltage is 0 V to VCC in the HIGH or LOW state."
      },
      {
        "number": "5",
        "name": "Q5",
        "type": "output",
        "description": "Parallel data output from storage register stage 5; output voltage is 0 V to VCC in the HIGH or LOW state."
      },
      {
        "number": "6",
        "name": "Q6",
        "type": "output",
        "description": "Parallel data output from storage register stage 6; output voltage is 0 V to VCC in the HIGH or LOW state."
      },
      {
        "number": "7",
        "name": "Q7",
        "type": "output",
        "description": "Parallel data output from storage register stage 7; output voltage is 0 V to VCC in the HIGH or LOW state."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground (0 V) reference for all voltages on the device."
      },
      {
        "number": "9",
        "name": "Q7S",
        "type": "output",
        "description": "Serial data output for cascading; it presents the previous contents of shift register stage 6 as the shift register is clocked."
      },
      {
        "number": "10",
        "name": "SHR",
        "type": "input",
        "description": "Shift register reset, active LOW; a LOW level clears only the shift register, and input voltage is rated 0 V to 5.5 V."
      },
      {
        "number": "11",
        "name": "SHCP",
        "type": "input",
        "description": "Shift register clock input; data is shifted on the LOW-to-HIGH transition, and inputs have Schmitt-trigger action."
      },
      {
        "number": "12",
        "name": "STCP",
        "type": "input",
        "description": "Storage register clock input; shift register contents are transferred to the storage register on the LOW-to-HIGH transition."
      },
      {
        "number": "13",
        "name": "STR",
        "type": "input",
        "description": "Storage register reset, active LOW; a LOW level clears only the storage register, and input voltage is rated 0 V to 5.5 V."
      },
      {
        "number": "14",
        "name": "DS",
        "type": "input",
        "description": "Serial data input to shift register stage 0; input voltage is rated 0 V to 5.5 V."
      },
      {
        "number": "15",
        "name": "Q0",
        "type": "output",
        "description": "Parallel data output from storage register stage 0; output voltage is 0 V to VCC in the HIGH or LOW state."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage; recommended 1.65 V to 3.6 V, with functional operation stated down to 1.2 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin numbering for TSSOP16 (SOT403-1) is taken from Table 2 and Fig. 5, which the datasheet shares wi; The datasheet does not explicitly label the Q0 to Q7 outputs as 3-state on the pin table; the 3-stat"
        ],
        "pages_sent": 18,
        "cost_usd": 0.0866,
        "at": "2026-10-19T04:57:30"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908360779370496",
        "pages": 18,
        "sha256": "2168810e07420481",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
        "checked": "2026-10-19",
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        "role": "eda",
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        "origin": "footprint origin = pad-pattern centre",
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        "sha256": "cddd954d592f9f1415686ad95650a8389959b080033a92919f40455df328d3ea",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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  }
}