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74LVC594APW

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Nexperia Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74LVC594APW

Nexperia · Shift Registers · TSSOP-16

74LVC594APW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 output Parallel data output from storage register stage 1; output voltage is 0 V to VCC in the HIGH or LOW state.
2 Q2 output Parallel data output from storage register stage 2; output voltage is 0 V to VCC in the HIGH or LOW state.
3 Q3 output Parallel data output from storage register stage 3; output voltage is 0 V to VCC in the HIGH or LOW state.
4 Q4 output Parallel data output from storage register stage 4; output voltage is 0 V to VCC in the HIGH or LOW state.
5 Q5 output Parallel data output from storage register stage 5; output voltage is 0 V to VCC in the HIGH or LOW state.
6 Q6 output Parallel data output from storage register stage 6; output voltage is 0 V to VCC in the HIGH or LOW state.
7 Q7 output Parallel data output from storage register stage 7; output voltage is 0 V to VCC in the HIGH or LOW state.
8 GND power_in Ground (0 V) reference for all voltages on the device.
9 Q7S output Serial data output for cascading; it presents the previous contents of shift register stage 6 as the shift register is clocked.
10 SHR input Shift register reset, active LOW; a LOW level clears only the shift register, and input voltage is rated 0 V to 5.5 V.
11 SHCP input Shift register clock input; data is shifted on the LOW-to-HIGH transition, and inputs have Schmitt-trigger action.
12 STCP input Storage register clock input; shift register contents are transferred to the storage register on the LOW-to-HIGH transition.
13 STR input Storage register reset, active LOW; a LOW level clears only the storage register, and input voltage is rated 0 V to 5.5 V.
14 DS input Serial data input to shift register stage 0; input voltage is rated 0 V to 5.5 V.
15 Q0 output Parallel data output from storage register stage 0; output voltage is 0 V to VCC in the HIGH or LOW state.
16 VCC power_in Supply voltage; recommended 1.65 V to 3.6 V, with functional operation stated down to 1.2 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 1.65 3.6 V 6
supply voltage (functional) VCC 1.2 V functional 6
input voltage VI 0 5.5 V 6
output voltage 3-state VO 0 5.5 V 3-state 6
output voltage HIGH or LOW state VO 0 V output HIGH or LOW state 6
ambient temperature Tamb -40 125 °C 6
input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 1.65 V to 2.7 V 6
input transition rise and fall rate Δt/ΔV 10 ns/V VCC = 2.7 V to 3.6 V 6
supply voltage VCC -0.5 6.5 V 5
input clamping current IIK -50 mA VI < 0 V 5
input voltage VI -0.5 6.5 V 5
output clamping current IOK -50 50 mA VO > VCC or VO < 0 V 5
output voltage 3-state VO -0.5 6.5 V 3-state 5
output voltage HIGH or LOW state VO -0.5 V output HIGH or LOW state 5
output current IO -50 50 mA VO = 0 V to VCC 5
supply current ICC 100 mA 5
ground current IGND -100 mA 5
storage temperature Tstg -65 150 °C 5
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 5
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V 6
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 6
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 6
LOW-level input voltage VIL 0.12 V VCC = 1.2 V 6
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 6
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 6
HIGH-level output voltage VOH 1.05 V VI = VIH or VIL; IO = -4 mA; VCC = 1.65 V 6
HIGH-level output voltage VOH 1.65 V VI = VIH or VIL; IO = -8 mA; VCC = 2.3 V 6
HIGH-level output voltage VOH 2.05 V VI = VIH or VIL; IO = -12 mA; VCC = 2.7 V 6
HIGH-level output voltage VOH 2.25 V VI = VIH or VIL; IO = -18 mA; VCC = 3.0 V 6
HIGH-level output voltage VOH 2 V VI = VIH or VIL; IO = -24 mA; VCC = 3.0 V 6
LOW-level output voltage VOL 0.3 V VI = VIH or VIL; IO = 100 μA; VCC = 1.65 V to 3.6 V 6
LOW-level output voltage VOL 0.65 V VI = VIH or VIL; IO = 4 mA; VCC = 1.65 V 6
LOW-level output voltage VOL 0.8 V VI = VIH or VIL; IO = 8 mA; VCC = 2.3 V 6
LOW-level output voltage VOL 0.6 V VI = VIH or VIL; IO = 12 mA; VCC = 2.7 V 6
input leakage current II -20 0.1 20 μA VCC = 3.6 V; VI = 5.5 V or GND 7
power-off leakage current IOFF 0.1 20 μA VCC = 0 V; VI or VO = 5.5 V 7
supply current ICC 0.1 40 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A 7
additional supply current ΔICC 5 5000 μA per input pin; VCC = 1.65 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 7
propagation delay SHCP to Q7S tpd 2 5.2 18.2 ns SHCP to Q7S; see Fig. 7; VCC = 1.65 V to 1.95 V 7
propagation delay SHCP to Q7S tpd 1.5 3.2 9.3 ns SHCP to Q7S; see Fig. 7; VCC = 2.3 V to 2.7 V 7
propagation delay SHCP to Q7S tpd 1.5 3.5 8.7 ns SHCP to Q7S; see Fig. 7; VCC = 2.7 V 7
propagation delay SHCP to Q7S tpd 1.5 3.1 7.7 ns SHCP to Q7S; see Fig. 7; VCC = 3.0 V to 3.6 V 7
propagation delay STCP to Qn tpd 2 7.6 18.2 ns STCP to Qn; see Fig. 8; VCC = 1.65 V to 1.95 V 7
propagation delay STCP to Qn tpd 1.5 4.8 9.3 ns STCP to Qn; see Fig. 8; VCC = 2.3 V to 2.7 V 7
propagation delay STCP to Qn tpd 1.5 5.2 8.7 ns STCP to Qn; see Fig. 8; VCC = 2.7 V 7
propagation delay STCP to Qn tpd 1.2 4.5 7.7 ns STCP to Qn; see Fig. 8; VCC = 3.0 V to 3.6 V 7
pulse width SHCP, STCP HIGH or LOW tW 7 2.5 ns SHCP, STCP HIGH or LOW; see Fig. 7 and Fig. 8; VCC = 1.65 V to 1.95 V 8
pulse width SHCP, STCP HIGH or LOW tW 5.5 2 ns SHCP, STCP HIGH or LOW; see Fig. 7 and Fig. 8; VCC = 2.3 V to 2.7 V 8
pulse width SHCP, STCP HIGH or LOW tW 5 1.5 ns SHCP, STCP HIGH or LOW; see Fig. 7 and Fig. 8; VCC = 2.7 V 8
pulse width SHCP, STCP HIGH or LOW tW 4.5 1.5 ns SHCP, STCP HIGH or LOW; see Fig. 7 and Fig. 8; VCC = 3.0 V to 3.6 V 8
set-up time DS to SHCP tsu 5.5 1 ns DS to SHCP; see Fig. 9; VCC = 1.65 V to 1.95 V 8
set-up time DS to SHCP tsu 4.5 0.8 ns DS to SHCP; see Fig. 9; VCC = 2.3 V to 2.7 V 8
set-up time DS to SHCP tsu 2.5 0.6 ns DS to SHCP; see Fig. 9; VCC = 2.7 V 8
maximum frequency fmax 70 130 MHz SHCP or STCP; see Fig. 7 and Fig. 8; VCC = 1.65 V to 1.95 V 8
maximum frequency fmax 90 140 MHz SHCP or STCP; see Fig. 7 and Fig. 8; VCC = 2.3 V to 2.7 V 8
maximum frequency fmax 100 150 MHz SHCP or STCP; see Fig. 7 and Fig. 8; VCC = 2.7 V 8
maximum frequency fmax 115 180 MHz SHCP or STCP; see Fig. 7 and Fig. 8; VCC = 3.0 V to 3.6 V 8
output skew time tsk(o) 1.5 ns VCC = 3.0 V to 3.6 V 9

CAD (KiCad official)

  • Symbol: 74LVC594APW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74lvc594apw-etched.step / 74lvc594apw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc594apw.step / 74lvc594apw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 2168810e07420481, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF