component
74LVC1G74DP-Q100H
Public Made by Adomby adom
Nexperia Flip Flops, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
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"version": "0.1.0",
"type": "component",
"description": "Nexperia Flip Flops, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
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"logic",
"74lvc1g74dp-q100h",
"factory-2.0.0",
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"component": {
"mpn": "74LVC1G74DP-Q100H",
"manufacturer": "Nexperia",
"package": "TSSOP-8",
"pin_count": 8,
"category": "Logic",
"subcategory": "Flip Flops",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588913599963648000",
"parts": {
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"lbr": "74lvc1g74dp-q100h.lbr"
},
"distributor_links": {
"lcsc": "C548409",
"digikey": "1727-7463-2-ND"
},
"distributor_check": {
"checked_at": "2026-10-17T16:07:20Z",
"source": "Component Ocean /api/assign-pns",
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"pn": "1727-7463-2-ND",
"status": "found"
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"pins": [
{
"number": "1",
"name": "CP",
"type": "input",
"description": "Clock input, edge-triggered on the LOW-to-HIGH transition; data at D that meets set-up and hold time around this transition is stored in the flip-flop."
},
{
"number": "2",
"name": "D",
"type": "input",
"description": "Data input, which must meet the set-up and hold time requirements around the LOW-to-HIGH clock transition (set-up 1.1 ns and hold 1.0 ns minimum at 4.5 V to 5.5 V)."
},
{
"number": "3",
"name": "Q",
"type": "output",
"description": "Complement output of the flip-flop (Q-bar), which is the inverse of the stored state."
},
{
"number": "4",
"name": "GND",
"type": "power_in",
"description": "Ground (0 V) reference for all voltages."
},
{
"number": "5",
"name": "Q",
"type": "output",
"description": "True (non-inverted) output of the flip-flop; the stored D value appears here after a LOW-to-HIGH clock transition."
},
{
"number": "6",
"name": "RD",
"type": "input",
"description": "Asynchronous reset-direct input, active LOW, which forces Q LOW and Q HIGH independently of the clock."
},
{
"number": "7",
"name": "SD",
"type": "input",
"description": "Asynchronous set-direct input, active LOW, which forces Q HIGH and Q LOW independently of the clock."
},
{
"number": "8",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage, recommended operating range 1.65 V to 5.5 V; absolute maximum VCC is -0.5 V to +6.5 V."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
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"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The text extraction shows both outputs as 'Q'; the overbar on pin 3 (complement output) is not prese; Set-up and hold values quoted in the description are the 4.5 V to 5.5 V figures from Table 9 (the se"
],
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"cost_usd": 0.0759,
"at": "2026-10-17T16:05:24"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588913599963648000",
"pages": 16,
"sha256": "19456f17233c9a5b",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
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"described": 8,
"cites_pages": true,
"refuses_to_fabricate": true
}
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}