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74LVC1G74DP-Q100H

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Nexperia Flip Flops, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC1G74DP-Q100H

Nexperia · Flip Flops · TSSOP-8

74LVC1G74DP-Q100H from Nexperia, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CP input Clock input, edge-triggered on the LOW-to-HIGH transition; data at D that meets set-up and hold time around this transition is stored in the flip-flop.
2 D input Data input, which must meet the set-up and hold time requirements around the LOW-to-HIGH clock transition (set-up 1.1 ns and hold 1.0 ns minimum at 4.5 V to 5.5 V).
3 Q output Complement output of the flip-flop (Q-bar), which is the inverse of the stored state.
4 GND power_in Ground (0 V) reference for all voltages.
5 Q output True (non-inverted) output of the flip-flop; the stored D value appears here after a LOW-to-HIGH clock transition.
6 RD input Asynchronous reset-direct input, active LOW, which forces Q LOW and Q HIGH independently of the clock.
7 SD input Asynchronous set-direct input, active LOW, which forces Q HIGH and Q LOW independently of the clock.
8 VCC power_in Supply voltage, recommended operating range 1.65 V to 5.5 V; absolute maximum VCC is -0.5 V to +6.5 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-8
Category Logic
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 6.5 V 4
input clamping current IIK -50 mA VI < 0 V 4
input voltage VI -0.5 6.5 V 4
output clamping current IOK -50 50 mA VO > VCC or VO < 0 V 4
output voltage VO -0.5 V Active mode 4
output voltage VO -0.5 6.5 V Power-down mode; VCC = 0 V 4
output current IO -50 50 mA VO = 0 V to VCC 4
supply current ICC 100 mA 4
ground current IGND -100 mA 4
total power dissipation Ptot 250 mW Tamb = -40 °C to +125 °C 4
storage temperature Tstg -65 150 °C 4
supply voltage VCC 1.65 5.5 V 4
input voltage VI 0 5.5 V 4
output voltage VO 0 V Active mode 4
output voltage VO 0 5.5 V Power-down mode; VCC = 0 V 4
ambient temperature Tamb -40 125 °C 4
input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 1.65 V to 2.7 V 4
input transition rise and fall rate Δt/ΔV 10 ns/V VCC = 2.7 V to 5.5 V 4
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 5
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 5
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 5
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 5
HIGH-level output voltage VOH 0.95 1.54 V VI = VIH or VIL; IO = -4 mA; VCC = 1.65 V 5
HIGH-level output voltage VOH 1.7 2.15 V VI = VIH or VIL; IO = -8 mA; VCC = 2.3 V 5
HIGH-level output voltage VOH 1.9 2.5 V VI = VIH or VIL; IO = -12 mA; VCC = 2.7 V 5
HIGH-level output voltage VOH 2 2.62 V VI = VIH or VIL; IO = -24 mA; VCC = 3.0 V 5
HIGH-level output voltage VOH 3.4 4.11 V VI = VIH or VIL; IO = -32 mA; VCC = 4.5 V 5
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO = 100 μA; VCC = 1.65 V to 5.5 V 5
LOW-level output voltage VOL 0.07 0.7 V VI = VIH or VIL; IO = 4 mA; VCC = 1.65 V 5
LOW-level output voltage VOL 0.12 0.45 V VI = VIH or VIL; IO = 8 mA; VCC = 2.3 V 5
LOW-level output voltage VOL 0.17 0.6 V VI = VIH or VIL; IO = 12 mA; VCC = 2.7 V 5
LOW-level output voltage VOL 0.33 0.8 V VI = VIH or VIL; IO = 24 mA; VCC = 3.0 V 5
LOW-level output voltage VOL 0.39 0.8 V VI = VIH or VIL; IO = 32 mA; VCC = 4.5 V 5
input leakage current II -1 1 μA VI = 5.5 V or GND; VCC = 0 V to 5.5 V 5
power-off leakage current IOFF -2 2 μA VI or VO = 5.5 V; VCC = 0 V 5
supply current ICC 0.1 4 μA VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A 5
additional supply current ΔICC 5 500 μA per pin; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V 5
CP to Q, Q propagation delay tpd 1.5 6 13.4 ns CP to Q, Q; see Fig. 6; VCC = 1.65 V to 1.95 V 6
CP to Q, Q propagation delay tpd 1 3.5 7.1 ns CP to Q, Q; see Fig. 6; VCC = 2.3 V to 2.7 V 6
CP to Q, Q propagation delay tpd 1 3.5 5.9 ns CP to Q, Q; see Fig. 6; VCC = 3.0 V to 3.6 V 6
CP to Q, Q propagation delay tpd 1 2.5 4.1 ns CP to Q, Q; see Fig. 6; VCC = 4.5 V to 5.5 V 6
set-up time tsu 2.9 ns D to CP; see Fig. 6; VCC = 1.65 V to 1.95 V 7
set-up time tsu 1.7 ns D to CP; see Fig. 6; VCC = 2.3 V to 2.7 V 7
set-up time tsu 1.3 0.5 ns D to CP; see Fig. 6; VCC = 3.0 V to 3.6 V 7
set-up time tsu 1.1 ns D to CP; see Fig. 6; VCC = 4.5 V to 5.5 V 7
hold time th 1.5 ns D to CP; see Fig. 6; VCC = 1.65 V to 1.95 V 7
hold time th 1 ns D to CP; see Fig. 6; VCC = 2.3 V to 2.7 V 7
hold time th 1 0.6 ns D to CP; see Fig. 6; VCC = 3.0 V to 3.6 V 7
maximum frequency fmax 80 MHz CP; see Fig. 6; VCC = 1.65 V to 1.95 V 7
maximum frequency fmax 175 MHz CP; see Fig. 6; VCC = 2.3 V to 2.7 V 7
maximum frequency fmax 175 280 MHz CP; see Fig. 6; VCC = 3.0 V to 3.6 V 7
maximum frequency fmax 200 MHz CP; see Fig. 6; VCC = 4.5 V to 5.5 V 7

CAD (KiCad official)

  • Symbol: 74LVC1G74DP-Q100H
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: 74lvc1g74dp-q100h-etched.step / 74lvc1g74dp-q100h-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc1g74dp-q100h.step / 74lvc1g74dp-q100h.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 19456f17233c9a5b, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF