74LVC1G00M7

{
  "schema_version": 1,
  "type": "component",
  "slug": "74lvc1g00m7",
  "title": "74LVC1G00M7",
  "brief": "HGSEMI Gates, SC-70-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "74lvc1g00m7"
  ],
  "component": {
    "mpn": "74LVC1G00M7",
    "manufacturer": "HGSEMI",
    "package": "SC-70-5",
    "pin_count": 5,
    "category": "Logic",
    "subcategory": "Gates",
    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312081749_HGSEMI-74LVC1G00M7-TR_C19193439.pdf",
    "parts": {
      "symbol": "74lvc1g00m7.kicad_sym",
      "footprint": "74lvc1g00m7.kicad_mod",
      "model_3d": "74lvc1g00m7-etched.glb",
      "model_3d_plain": "74lvc1g00m7.glb",
      "model_3d_step": "74lvc1g00m7-etched.step",
      "model_3d_step_plain": "74lvc1g00m7.step",
      "lbr": "74lvc1g00m7.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "A",
        "type": "input",
        "description": "Logic input A of the 2-input NAND gate. CMOS input; VIH ≥ 0.7*VCC and VIL ≤ 0.3*VCC at VCC = 3-5.5 V. Input leakage current ~0.01 uA typ (±5 uA max)."
      },
      {
        "number": "2",
        "name": "B",
        "type": "input",
        "description": "Logic input B of the 2-input NAND gate. CMOS input; VIH ≥ 0.7*VCC and VIL ≤ 0.3*VCC at VCC = 3-5.5 V. Input leakage current ~0.01 uA typ (±5 uA max)."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V) for the device."
      },
      {
        "number": "4",
        "name": "Y",
        "type": "output",
        "description": "NAND gate output: Y = NOT(A AND B). Push-pull CMOS output; sources up to 32 mA and sinks up to 32 mA at VCC = 4.5 V. Absolute max per-pin output current 25 mA (recommended)."
      },
      {
        "number": "5",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply input. Operating range 1.65 V to 5.5 V; absolute maximum 6.5 V. Bypass with a ceramic capacitor placed close to the pin."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312081749_HGSEMI-74LVC1G00M7-TR_C19193439.pdf",
        "pages": 8,
        "sha256": "c6654ee8f8b8fc1b",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 5,
        "described": 5,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74LVC1G00",
      "logic_family": "74LVC",
      "function_code": "1G00",
      "function_class": "Gate",
      "function_name": "1-gate variant of Quad 2-Input NAND Gate (00)",
      "manufacturer": null,
      "is_specialty": false
    },
    "models_3d": [
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        "file": "74lvc1g00m7.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          2.1,
          2.0,
          1.1
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "2860de5b7b085919ff6e952148353f928798588d9f544dc69430545aff2ba908",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "74lvc1g00m7-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          1.1
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "96e718bda067cbe5b5db3c535d2da583d1c706050ac00a546dbdca7ddf92d544",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "HGSEMI",
      "Package": "SC-70-5",
      "Category": "Logic",
      "Pins": "5"
    }
  },
  "variants": [
    {
      "mpn": "74LVC1G00M7",
      "kind": "packaging"
    },
    {
      "mpn": "74LVC1G00M7/TR",
      "kind": "packaging"
    },
    {
      "mpn": "74LVC1G00M7M5",
      "kind": "packaging"
    },
    {
      "mpn": "74LVC1G00M7M5/TR",
      "kind": "packaging"
    }
  ],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "74lvc1g00m7"
  ],
  "discovery_pitch": "74LVC1G00M7 (HGSEMI) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "74lvc1g00m7.step",
    "74lvc1g00m7.lbr",
    "docs/hero.png",
    "docs/74lvc1g00m7-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T15:09:25.529Z"
}