component

74LVC1G00M7

Public Made by Adom

by adom

HGSEMI Gates, SC-70-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs 74lvc1g00m7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers 74lvc1g00m7: viewers · Ray 2mo ago
74lvc1g00m7-etched.fit.json 74lvc1g00m7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74lvc1g00m7-etched.glb 74lvc1g00m7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74lvc1g00m7-etched.step 74lvc1g00m7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74lvc1g00m7.glb Publish 0.1.0 · Ray 2mo ago
74lvc1g00m7.kicad_mod Publish 0.1.0 · Ray 2mo ago
74lvc1g00m7.kicad_sym Publish 0.1.0 · Ray 2mo ago
74lvc1g00m7.lbr Publish 0.1.0 · Ray 2mo ago
74lvc1g00m7.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.1.0 · Ray 2mo ago
page.json 74lvc1g00m7: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 28d ago
README.md 74lvc1g00m7: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

74LVC1G00M7

HGSEMI · Gates · SC-70-5

74LVC1G00M7 from HGSEMI, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Logic input A of the 2-input NAND gate. CMOS input; VIH ≥ 0.7VCC and VIL ≤ 0.3VCC at VCC = 3-5.5 V. Input leakage current ~0.01 uA typ (±5 uA max).
2 B input Logic input B of the 2-input NAND gate. CMOS input; VIH ≥ 0.7VCC and VIL ≤ 0.3VCC at VCC = 3-5.5 V. Input leakage current ~0.01 uA typ (±5 uA max).
3 GND power_in Ground reference (0 V) for the device.
4 Y output NAND gate output: Y = NOT(A AND B). Push-pull CMOS output; sources up to 32 mA and sinks up to 32 mA at VCC = 4.5 V. Absolute max per-pin output current 25 mA (recommended).
5 VCC power_in Positive supply input. Operating range 1.65 V to 5.5 V; absolute maximum 6.5 V. Bypass with a ceramic capacitor placed close to the pin.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package SC-70-5
Category Logic
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • 74LVC1G00M7
  • 74LVC1G00M7/TR
  • 74LVC1G00M7M5
  • 74LVC1G00M7M5/TR

CAD (KiCad official)

  • Symbol: 74LVC1G00M7
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SC-70-5 (KiCad packages3D, STEP)
  • 3D model files: 74lvc1g00m7-etched.step / 74lvc1g00m7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc1g00m7.step / 74lvc1g00m7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (8 pp, sha256 c6654ee8f8b8fc1b, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF