74lvc1g00dbvrg: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC b…
74lvc1g00dbvrg: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout")
74lvc1g00dbvrg: laser-etched CAD + chip hero (factory 2.0.0 backfill)
74lvc1g00dbvrg: stamp component.logic (74LVC1G00) from component-ocean
74lvc1g00dbvrg: factory component page (tier=lcsc)
Initial commit: component/74lvc1g00dbvrg