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74LV165AD

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Nexperia Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LV165AD

Nexperia · Shift Registers · SOIC-16

74LV165AD from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PL input Parallel enable input (active LOW); when LOW, data on D0 to D7 is loaded into the register asynchronously.
2 CP input Clock input, LOW-to-HIGH edge-triggered; CE should only make its LOW-to-HIGH transition while CP is HIGH for predictable operation.
3 D4 input Parallel data input D4, loaded into the register when PL is LOW.
4 D5 input Parallel data input D5, loaded into the register when PL is LOW.
5 D6 input Parallel data input D6, loaded into the register when PL is LOW.
6 D7 input Parallel data input D7, loaded into the register when PL is LOW.
7 Q7 (complementary) output Complementary serial output from the last stage (inverted Q7).
8 GND power_in Ground (0 V).
9 Q7 output Serial output from the last stage; can be tied to DS of the succeeding stage for expansion.
10 DS input Serial data input; data enters the register serially when PL is HIGH.
11 D0 input Parallel data input D0, loaded into the register when PL is LOW.
12 D1 input Parallel data input D1, loaded into the register when PL is LOW.
13 D2 input Parallel data input D2, loaded into the register when PL is LOW.
14 D3 input Parallel data input D3, loaded into the register when PL is LOW.
15 CE input Clock enable input (active LOW); the clock input is gated by this pin.
16 VCC power_in Positive supply voltage, 2.0 V to 5.5 V recommended operating range.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply voltage (absolute maximum) VCC -0.5 7 V 5
Input clamping current IIK -20 mA VI < 0 V 5
Input voltage (absolute maximum) VI -0.5 7 V 5
Output clamping current IOK -50 50 mA VO > VCC or VO < 0 5
Output voltage (absolute maximum) VO -0.5 V 5
Voltage in power-down mode (absolute maximum) -0.5 7 V power-down mode 5
Output current IO -25 25 mA 0 V < VO < VCC 5
Supply current (absolute maximum) ICC 50 mA 5
Ground current IGND -50 mA 5
Storage temperature Tstg -65 150 °C 5
Total power dissipation Ptot 500 mW Tamb = -40 °C to +85 °C 5
Supply voltage (recommended) VCC 2 5.5 V 5
Input voltage (recommended) VI 0 5.5 V 5
Output voltage (recommended) VO 0 V 5
Ambient temperature Tamb -40 85 °C 5
Input transition rise and fall rate Δt/ΔV 0 200 ns/V VCC = 2.3 V to 2.7 V 5
Input transition rise and fall rate Δt/ΔV 0 100 ns/V VCC = 3.0 V to 3.6 V 5
Input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 4.5 V to 5.5 V 5
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V 5
LOW-level input voltage VIL 0.5 V VCC = 2.0 V 5
HIGH-level output voltage VOH 2 V VI = VIH or VIL; IO = -2.0 mA; VCC = 2.3 V 6
HIGH-level output voltage VOH 2.48 V VI = VIH or VIL; IO = -6.0 mA; VCC = 3.0 V 6
HIGH-level output voltage VOH 3.8 V VI = VIH or VIL; IO = -12 mA; VCC = 4.5 V 6
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V to 5.5 V 6
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; IO = 2.0 mA; VCC = 2.3 V 6
LOW-level output voltage VOL 0.44 V VI = VIH or VIL; IO = 6.0 mA; VCC = 3.0 V 6
LOW-level output voltage VOL 0.55 V VI = VIH or VIL; IO = 12 mA; VCC = 4.5 V 6
Input leakage current II -1 0.01 1 μA VI = VCC or GND; VCC = 5.5 V 6
Power-off leakage current IOFF -5 0.05 5 μA VI or VO = 5.5 V; VCC = 0.0 V 6
Supply current ICC 0.2 20 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V 6
Propagation delay CE, CP to Q7, Q7 tpd 1 11 22 ns CE, CP to Q7, Q7; CL = 15 pF; VCC = 2.3 V to 2.7 V 7
Propagation delay CE, CP to Q7, Q7 tpd 1 7.5 18 ns CE, CP to Q7, Q7; CL = 15 pF; VCC = 3.0 V to 3.6 V 7
Propagation delay CE, CP to Q7, Q7 tpd 1 5.5 11.5 ns CE, CP to Q7, Q7; CL = 15 pF; VCC = 4.5 V to 5.5 V 7
Propagation delay PL to Q7, Q7 tpd 1 11.5 23.5 ns PL to Q7, Q7; CL = 15 pF; VCC = 2.3 V to 2.7 V 7
Propagation delay PL to Q7, Q7 tpd 1 8 18.5 ns PL to Q7, Q7; CL = 15 pF; VCC = 3.0 V to 3.6 V 7
Propagation delay PL to Q7, Q7 tpd 1 5.5 11.5 ns PL to Q7, Q7; CL = 15 pF; VCC = 4.5 V to 5.5 V 7
Propagation delay D7 to Q7, Q7 tpd 1 12 24 ns D7 to Q7, Q7; CL = 15 pF; VCC = 2.3 V to 2.7 V 7
Propagation delay D7 to Q7, Q7 tpd 1 8.5 16.5 ns D7 to Q7, Q7; CL = 15 pF; VCC = 3.0 V to 3.6 V 7
Propagation delay D7 to Q7, Q7 tpd 1 6 10.5 ns D7 to Q7, Q7; CL = 15 pF; VCC = 4.5 V to 5.5 V 7
Propagation delay CE, CP to Q7, Q7 tpd 1 13 26 ns CE, CP to Q7, Q7; VCC = 2.3 V to 2.7 V 7
Propagation delay CE, CP to Q7, Q7 tpd 1 9 21.5 ns CE, CP to Q7, Q7; VCC = 3.0 V to 3.6 V 7
Propagation delay CE, CP to Q7, Q7 tpd 1 6.1 13.5 ns CE, CP to Q7, Q7; VCC = 4.5 V to 5.5 V 7
Propagation delay PL to Q7, Q7 tpd 1 14 28 ns PL to Q7, Q7; see Fig. 7; VCC = 2.3 V to 2.7 V 7
Propagation delay PL to Q7, Q7 tpd 1 10 22 ns PL to Q7, Q7; see Fig. 7; VCC = 3.0 V to 3.6 V 7
Propagation delay PL to Q7, Q7 tpd 1 6.5 13.5 ns PL to Q7, Q7; see Fig. 7; VCC = 4.5 V to 5.5 V 7
Propagation delay D7 to Q7, Q7 tpd 1 14 28 ns D7 to Q7, Q7; see Fig. 8; VCC = 2.3 V to 2.7 V 7
Propagation delay D7 to Q7, Q7 tpd 1 10 20 ns D7 to Q7, Q7; see Fig. 8; VCC = 3.0 V to 3.6 V 7
Propagation delay D7 to Q7, Q7 tpd 1 6.5 12.5 ns D7 to Q7, Q7; see Fig. 8; VCC = 4.5 V to 5.5 V 7
CP pulse width (HIGH to LOW) tW 9 ns CP input HIGH to LOW; see Fig. 6; VCC = 2.3 V to 2.7 V 7
CP pulse width (HIGH to LOW) tW 7 ns CP input HIGH to LOW; see Fig. 6; VCC = 3.0 V to 3.6 V 7
CP pulse width (HIGH to LOW) tW 4 ns CP input HIGH to LOW; see Fig. 6; VCC = 4.5 V to 5.5 V 7
PL pulse width (LOW) tW 13 ns PL input LOW; see Fig. 7; VCC = 2.3 V to 2.7 V 7
PL pulse width (LOW) tW 9 ns PL input LOW; see Fig. 7; VCC = 3.0 V to 3.6 V 7
PL pulse width (LOW) tW 6 ns PL input LOW; see Fig. 7; VCC = 4.5 V to 5.5 V 7
Recovery time PL to CP, CE trec 8.5 ns PL to CP, CE; see Fig. 7; VCC = 2.3 V to 2.7 V 7
Recovery time PL to CP, CE trec 6 ns PL to CP, CE; see Fig. 7; VCC = 3.0 V to 3.6 V 7
Recovery time PL to CP, CE trec 4 ns PL to CP, CE; see Fig. 7; VCC = 4.5 V to 5.5 V 7
Maximum clock frequency (CL = 15 pF) fmax 45 80 MHz CP input; CL = 15 pF; see Fig. 6; VCC = 2.3 V to 2.7 V 8
Maximum clock frequency (CL = 15 pF) fmax 50 115 MHz CP input; CL = 15 pF; see Fig. 6; VCC = 3.0 V to 3.6 V 8
Maximum clock frequency (CL = 15 pF) fmax 90 165 MHz CP input; CL = 15 pF; see Fig. 6; VCC = 4.5 V to 5.5 V 8

CAD (KiCad official)

  • Symbol: 74LV165AD
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 74lv165ad-etched.step / 74lv165ad-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lv165ad.step / 74lv165ad.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 5200e6b7998d1565, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF