component
74HCT32BQ-Q100
Public Made by Adomby adom
Nexperia Gates, DHVQFN-14(2.5x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
74HCT32BQ-Q100
Nexperia · Gates · DHVQFN-14(2.5x3)
74HCT32BQ-Q100 from Nexperia, in a DHVQFN-14(2.5x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input A of OR gate 1; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 2 | 1B | input | Data input B of OR gate 1; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 3 | 1Y | output | Data output of OR gate 1, where Y = A OR B per the function table. |
| 4 | 2A | input | Data input A of OR gate 2; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 5 | 2B | input | Data input B of OR gate 2; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 6 | 2Y | output | Data output of OR gate 2, where Y = A OR B per the function table. |
| 7 | GND | power_in | Ground (0 V) reference; all voltages in the datasheet are referenced to this pin. |
| 8 | 3Y | output | Data output of OR gate 3, where Y = A OR B per the function table. |
| 9 | 3A | input | Data input A of OR gate 3; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 10 | 3B | input | Data input B of OR gate 3; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 11 | 4Y | output | Data output of OR gate 4, where Y = A OR B per the function table. |
| 12 | 4A | input | Data input A of OR gate 4; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 13 | 4B | input | Data input B of OR gate 4; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 14 | VCC | power_in | Supply voltage: 2.0 V to 6.0 V for 74HC32-Q100 and 4.5 V to 5.5 V for 74HCT32-Q100 per recommended operating conditions; absolute maximum +7 V. |
| 15 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | DHVQFN-14(2.5x3) |
| Category | Logic ICs |
| Pins | 15 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| Input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V [1] | 3 | |
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V [1] | 3 | |
| Output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 3 | |
| Supply current | ICC | 50 | mA | 3 | |||
| Ground current | IGND | -50 | mA | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Total power dissipation | Ptot | 500 | mW | [2] DHVQFN14 (SOT762-1): derates linearly 9.6 mW/K above 98 °C | 3 | ||
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 74HCT32-Q100 | 3 |
| Input voltage | VI | 0 | V | Maximum printed as VCC | 3 | ||
| Output voltage | VO | 0 | V | Maximum printed as VCC | 3 | ||
| Ambient temperature | Tamb | -40 | 125 | °C | 3 | ||
| Input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 3 | |
| HIGH-level input voltage | VIH | 2 | 1.6 | V | VCC = 4.5 V to 5.5 V; 25 °C | 4 | |
| HIGH-level input voltage | VIH | 2 | V | VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 4 | ||
| LOW-level input voltage | VIL | 1.2 | 0.8 | V | VCC = 4.5 V to 5.5 V; 25 °C | 4 | |
| LOW-level input voltage | VIL | 0.8 | V | VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 4 | ||
| HIGH-level output voltage (IO = -20 µA) | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; 25 °C | 4 | |
| HIGH-level output voltage (IO = -20 µA) | VOH | 4.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; -40 °C to +85 °C | 4 | ||
| HIGH-level output voltage (IO = -4.0 mA) | VOH | 3.98 | 4.32 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; 25 °C | 4 | |
| HIGH-level output voltage (IO = -4.0 mA) | VOH | 3.84 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; -40 °C to +85 °C | 4 | ||
| HIGH-level output voltage (IO = -4.0 mA) | VOH | 3.7 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; -40 °C to +125 °C | 4 | ||
| LOW-level output voltage (IO = 20 µA) | VOL | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; 25 °C | 4 | |
| LOW-level output voltage (IO = 20 µA) | VOL | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; -40 °C to +85 °C | 4 | ||
| LOW-level output voltage (IO = 5.2 mA) | VOL | 0.15 | 0.25 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 5.2 mA; 25 °C | 4 | |
| LOW-level output voltage (IO = 5.2 mA) | VOL | 0.33 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 5.2 mA; -40 °C to +85 °C | 4 | ||
| LOW-level output voltage (IO = 5.2 mA) | VOL | 0.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 5.2 mA; -40 °C to +125 °C | 4 | ||
| Input leakage current | II | -0.1 | 0.1 | μA | VI = VCC or GND; VCC = 5.5 V; 25 °C | 5 | |
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 5.5 V; -40 °C to +85 °C | 5 | |
| Supply current | ICC | 2 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C | 5 | ||
| Supply current | ICC | 20 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +85 °C | 5 | ||
| Supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C | 5 | ||
| Additional supply current per input pin | ΔICC | 430 | μA | Per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C | 5 | ||
| Additional supply current per input pin | ΔICC | 540 | μA | Per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 5 | ||
| Additional supply current per input pin | ΔICC | 590 | μA | Per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 5 | ||
| Propagation delay nA, nB to nY | tpd | 11 | 24 | ns | nA, nB to nY; VCC = 4.5 V; CL = 50 pF; see Fig. 6; 25 °C | 5 | |
| Propagation delay nA, nB to nY | tpd | 30 | ns | nA, nB to nY; VCC = 4.5 V; CL = 50 pF; see Fig. 6; -40 °C to +85 °C | 5 | ||
| Propagation delay nA, nB to nY | tpd | 36 | ns | nA, nB to nY; VCC = 4.5 V; CL = 50 pF; see Fig. 6; -40 °C to +125 °C | 5 | ||
| Transition time | tt | 7 | 15 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 6; 25 °C | 5 | |
| Transition time | tt | 19 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 6; -40 °C to +85 °C | 5 | ||
| Transition time | tt | 22 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 6; -40 °C to +125 °C | 5 |
CAD (KiCad official)
- Symbol:
74HCT32BQ-Q100 - Footprint:
Package_DFN_QFN:DHVQFN-14-1EP_2.5x3mm_P0.5mm_EP1x1.5mm - 3D model: DHVQFN-14(2.5x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
74hct32bq-q100-etched.step/74hct32bq-q100-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hct32bq-q100.step/74hct32bq-q100.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
7298aa3d0ab9a5ee, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74HCT32BQ-Q100
**Nexperia** · Gates · DHVQFN-14(2.5x3)
74HCT32BQ-Q100 from Nexperia, in a DHVQFN-14(2.5x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input A of OR gate 1; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 2 | 1B | input | Data input B of OR gate 1; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 3 | 1Y | output | Data output of OR gate 1, where Y = A OR B per the function table. |
| 4 | 2A | input | Data input A of OR gate 2; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 5 | 2B | input | Data input B of OR gate 2; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 6 | 2Y | output | Data output of OR gate 2, where Y = A OR B per the function table. |
| 7 | GND | power_in | Ground (0 V) reference; all voltages in the datasheet are referenced to this pin. |
| 8 | 3Y | output | Data output of OR gate 3, where Y = A OR B per the function table. |
| 9 | 3A | input | Data input A of OR gate 3; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 10 | 3B | input | Data input B of OR gate 3; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 11 | 4Y | output | Data output of OR gate 4, where Y = A OR B per the function table. |
| 12 | 4A | input | Data input A of OR gate 4; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 13 | 4B | input | Data input B of OR gate 4; inputs include clamp diodes, so current-limiting resistors can be used to interface voltages above VCC. |
| 14 | VCC | power_in | Supply voltage: 2.0 V to 6.0 V for 74HC32-Q100 and 4.5 V to 5.5 V for 74HCT32-Q100 per recommended operating conditions; absolute maximum +7 V. |
| 15 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | DHVQFN-14(2.5x3) |
| Category | Logic ICs |
| Pins | 15 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | -0.5 | | 7 | V | | 3 |
| Input clamping current | IIK | -20 | | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V [1] | 3 |
| Output clamping current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V [1] | 3 |
| Output current | IO | -25 | | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 3 |
| Supply current | ICC | | | 50 | mA | | 3 |
| Ground current | IGND | -50 | | | mA | | 3 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| Total power dissipation | Ptot | | | 500 | mW | [2] DHVQFN14 (SOT762-1): derates linearly 9.6 mW/K above 98 °C | 3 |
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 74HCT32-Q100 | 3 |
| Input voltage | VI | 0 | | | V | Maximum printed as VCC | 3 |
| Output voltage | VO | 0 | | | V | Maximum printed as VCC | 3 |
| Ambient temperature | Tamb | -40 | | 125 | °C | | 3 |
| Input transition rise and fall rate | Δt/ΔV | | 1.67 | 139 | ns/V | VCC = 4.5 V | 3 |
| HIGH-level input voltage | VIH | 2 | 1.6 | | V | VCC = 4.5 V to 5.5 V; 25 °C | 4 |
| HIGH-level input voltage | VIH | 2 | | | V | VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 4 |
| LOW-level input voltage | VIL | | 1.2 | 0.8 | V | VCC = 4.5 V to 5.5 V; 25 °C | 4 |
| LOW-level input voltage | VIL | | | 0.8 | V | VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 4 |
| HIGH-level output voltage (IO = -20 µA) | VOH | 4.4 | 4.5 | | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; 25 °C | 4 |
| HIGH-level output voltage (IO = -20 µA) | VOH | 4.4 | | | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; -40 °C to +85 °C | 4 |
| HIGH-level output voltage (IO = -4.0 mA) | VOH | 3.98 | 4.32 | | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; 25 °C | 4 |
| HIGH-level output voltage (IO = -4.0 mA) | VOH | 3.84 | | | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; -40 °C to +85 °C | 4 |
| HIGH-level output voltage (IO = -4.0 mA) | VOH | 3.7 | | | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; -40 °C to +125 °C | 4 |
| LOW-level output voltage (IO = 20 µA) | VOL | | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; 25 °C | 4 |
| LOW-level output voltage (IO = 20 µA) | VOL | | | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; -40 °C to +85 °C | 4 |
| LOW-level output voltage (IO = 5.2 mA) | VOL | | 0.15 | 0.25 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 5.2 mA; 25 °C | 4 |
| LOW-level output voltage (IO = 5.2 mA) | VOL | | | 0.33 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 5.2 mA; -40 °C to +85 °C | 4 |
| LOW-level output voltage (IO = 5.2 mA) | VOL | | | 0.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 5.2 mA; -40 °C to +125 °C | 4 |
| Input leakage current | II | -0.1 | | 0.1 | μA | VI = VCC or GND; VCC = 5.5 V; 25 °C | 5 |
| Input leakage current | II | -1 | | 1 | μA | VI = VCC or GND; VCC = 5.5 V; -40 °C to +85 °C | 5 |
| Supply current | ICC | | | 2 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C | 5 |
| Supply current | ICC | | | 20 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +85 °C | 5 |
| Supply current | ICC | | | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C | 5 |
| Additional supply current per input pin | ΔICC | | | 430 | μA | Per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C | 5 |
| Additional supply current per input pin | ΔICC | | | 540 | μA | Per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 5 |
| Additional supply current per input pin | ΔICC | | | 590 | μA | Per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 5 |
| Propagation delay nA, nB to nY | tpd | | 11 | 24 | ns | nA, nB to nY; VCC = 4.5 V; CL = 50 pF; see Fig. 6; 25 °C | 5 |
| Propagation delay nA, nB to nY | tpd | | | 30 | ns | nA, nB to nY; VCC = 4.5 V; CL = 50 pF; see Fig. 6; -40 °C to +85 °C | 5 |
| Propagation delay nA, nB to nY | tpd | | | 36 | ns | nA, nB to nY; VCC = 4.5 V; CL = 50 pF; see Fig. 6; -40 °C to +125 °C | 5 |
| Transition time | tt | | 7 | 15 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 6; 25 °C | 5 |
| Transition time | tt | | | 19 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 6; -40 °C to +85 °C | 5 |
| Transition time | tt | | | 22 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 6; -40 °C to +125 °C | 5 |
## CAD (KiCad official)
- Symbol: `74HCT32BQ-Q100`
- Footprint: `Package_DFN_QFN:DHVQFN-14-1EP_2.5x3mm_P0.5mm_EP1x1.5mm`
- 3D model: DHVQFN-14(2.5x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `74hct32bq-q100-etched.step` / `74hct32bq-q100-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hct32bq-q100.step` / `74hct32bq-q100.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74HCT32BQ-Q100.pdf) (12 pp, sha256 `7298aa3d0ab9a5ee`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74hct32bq-q100-datasheet.pdf)