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74HC595

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GR Shift Registers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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74HC595

GR · Shift Registers · SOP-16

74HC595 from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 QB tri_state Parallel data output bit B (Q1). One of eight 3-state latched parallel outputs; drives typ. 6 mA @ VCC=4.5 V and 7.8 mA @ VCC=6 V.
2 QC tri_state Parallel data output bit C (Q2). Latched 3-state output; enabled when /G is low, high-Z when /G is high.
3 QD tri_state Parallel data output bit D (Q3). Latched 3-state output.
4 QE tri_state Parallel data output bit E (Q4). Latched 3-state output.
5 QF tri_state Parallel data output bit F (Q5). Latched 3-state output.
6 QG tri_state Parallel data output bit G (Q6). Latched 3-state output.
7 QH tri_state Parallel data output bit H (Q7). Latched 3-state output; final stage of the storage register.
8 GND power_in Ground reference (0 V). Absolute-max GND current ±70 mA.
9 Q'H output Serial data output (QH'). Reflects the last stage of the shift register (Qn-1) so multiple 74HC595 devices can be cascaded to build 8n-bit SPI-style parallel outputs. Not 3-state; drives typ. 4 mA @ 4.5 V.
10 ~SCLR input Active-low shift register asynchronous clear. When SCLR = L (with /G low), all shift-register bits are cleared to 0 and Q'H = 0. Must be high for normal shifting.
11 SCK input Shift-register clock input. On the rising edge, SER is loaded into stage 0 and the shift register advances toward Q'H. Max frequency 10 MHz @ VCC=5 V; min pulse width 20 ns.
12 RCK input Storage/latch clock (register clock). Rising edge transfers the 8-bit shift-register contents into the output storage latches, which then appear on QA-QH (when /G is low).
13 ~G input Active-low output enable for the QA-QH 3-state parallel outputs. /G = L drives QA-QH from the latches; /G = H forces QA-QH to high-Z. Does not affect Q'H or the shift-register contents.
14 SER input Serial data input. Sampled on the rising edge of SCK and shifted into stage 0 of the 8-bit shift register. Setup time 20 ns, hold time 5 ns to SCK.
15 QA tri_state Parallel data output bit A (Q0). First bit of the 8-bit latched 3-state parallel output; drives typ. 6 mA @ VCC=4.5 V.
16 VCC power_in Positive supply, 2 V to 6 V (absolute max −0.5 V to 6.5 V). Quiescent ICC ≤ 5 µA @ VCC = 6 V. Decouple to GND with a local 0.1 µF capacitor.

Key specifications

Parameter Value
Manufacturer GR
Package SOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: 74HC595
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GR datasheet (9 pp, sha256 16ad2e36da69628c, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF