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74HC377D

Public Made by Adom

by adom

Nexperia Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC377D

Nexperia · Flip Flops · SOIC-20-300mil

74HC377D from Nexperia, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 E input Data enable input, active LOW: when E is LOW the outputs Qn take the state of Dn at the LOW-to-HIGH CP transition, and E must be stable one set-up time before that transition.
2 Q0 output Flip-flop output 0, which assumes the state of D0 on the LOW-to-HIGH clock transition when E is LOW.
3 D0 input Data input 0, sampled on the LOW-to-HIGH CP transition within the set-up and hold times; inputs include clamp diodes so input voltages above VCC are allowed with a current limiting resistor (IIK limited to ±20 mA).
4 D1 input Data input 1, sampled on the LOW-to-HIGH CP transition within the set-up and hold times; inputs include clamp diodes so input voltages above VCC are allowed with a current limiting resistor (IIK limited to ±20 mA).
5 Q1 output Flip-flop output 1, which assumes the state of D1 on the LOW-to-HIGH clock transition when E is LOW.
6 Q2 output Flip-flop output 2, which assumes the state of D2 on the LOW-to-HIGH clock transition when E is LOW.
7 D2 input Data input 2, sampled on the LOW-to-HIGH CP transition within the set-up and hold times; inputs include clamp diodes so input voltages above VCC are allowed with a current limiting resistor (IIK limited to ±20 mA).
8 D3 input Data input 3, sampled on the LOW-to-HIGH CP transition within the set-up and hold times; inputs include clamp diodes so input voltages above VCC are allowed with a current limiting resistor (IIK limited to ±20 mA).
9 Q3 output Flip-flop output 3, which assumes the state of D3 on the LOW-to-HIGH clock transition when E is LOW.
10 GND power_in Ground (0 V) reference for all voltages on the device.
11 CP input Clock input, edge triggered on the LOW-to-HIGH transition; the Qn outputs update only on this edge.
12 Q4 output Flip-flop output 4, which assumes the state of D4 on the LOW-to-HIGH clock transition when E is LOW.
13 D4 input Data input 4, sampled on the LOW-to-HIGH CP transition within the set-up and hold times; inputs include clamp diodes so input voltages above VCC are allowed with a current limiting resistor (IIK limited to ±20 mA).
14 D5 input Data input 5, sampled on the LOW-to-HIGH CP transition within the set-up and hold times; inputs include clamp diodes so input voltages above VCC are allowed with a current limiting resistor (IIK limited to ±20 mA).
15 Q5 output Flip-flop output 5, which assumes the state of D5 on the LOW-to-HIGH clock transition when E is LOW.
16 Q6 output Flip-flop output 6, which assumes the state of D6 on the LOW-to-HIGH clock transition when E is LOW.
17 D6 input Data input 6, sampled on the LOW-to-HIGH CP transition within the set-up and hold times; inputs include clamp diodes so input voltages above VCC are allowed with a current limiting resistor (IIK limited to ±20 mA).
18 D7 input Data input 7, sampled on the LOW-to-HIGH CP transition within the set-up and hold times; inputs include clamp diodes so input voltages above VCC are allowed with a current limiting resistor (IIK limited to ±20 mA).
19 Q7 output Flip-flop output 7, which assumes the state of D7 on the LOW-to-HIGH clock transition when E is LOW.
20 VCC power_in Supply voltage: 2.0 V to 6.0 V for 74HC377 and 4.5 V to 5.5 V for 74HCT377 recommended, with an absolute maximum of -0.5 V to +7 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-20-300mil
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 4
supply current ICC 50 mA 4
ground current IGND -50 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
supply voltage (74HC377 column) VCC 2 5 6 V 74HC377 column 4
input voltage VI 0 V max printed as VCC 4
output voltage VO 0 V max printed as VCC 4
ambient temperature Tamb -40 125 °C 74HC377 column 4
input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 4
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 4
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V; -40 °C to +85 °C 5
HIGH-level input voltage VIH 3.15 V VCC = 4.5 V; -40 °C to +85 °C 5
HIGH-level input voltage VIH 4.2 V VCC = 6.0 V; -40 °C to +85 °C 5
LOW-level input voltage VIL 0.5 V VCC = 2.0 V; -40 °C to +85 °C 5
LOW-level input voltage VIL 1.35 V VCC = 4.5 V; -40 °C to +85 °C 5
LOW-level input voltage VIL 1.8 V VCC = 6.0 V; -40 °C to +85 °C 5
HIGH-level output voltage VOH 1.9 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; -40 °C to +85 °C 5
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +85 °C 5
HIGH-level output voltage VOH 5.9 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; -40 °C to +85 °C 5
HIGH-level output voltage VOH 3.84 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +85 °C 5
HIGH-level output voltage VOH 5.34 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; -40 °C to +85 °C 5
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +85 °C 5
LOW-level output voltage VOL 0.33 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +85 °C 5
input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; -40 °C to +85 °C 5
supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +85 °C 5
propagation delay CP to Qn tpd 200 ns CP to Qn; see Fig. 6; VCC = 2.0 V; CL = 50 pF; -40 °C to +85 °C 7
propagation delay CP to Qn tpd 40 ns CP to Qn; see Fig. 6; VCC = 4.5 V; CL = 50 pF; -40 °C to +85 °C 7
propagation delay CP to Qn tpd 34 ns CP to Qn; see Fig. 6; VCC = 6.0 V; CL = 50 pF; -40 °C to +85 °C 7
output transition time tt 95 ns Qn output; see Fig. 6; VCC = 2.0 V; CL = 50 pF; -40 °C to +85 °C 7
output transition time tt 19 ns Qn output; see Fig. 6; VCC = 4.5 V; CL = 50 pF; -40 °C to +85 °C 7
output transition time tt 16 ns Qn output; see Fig. 6; VCC = 6.0 V; CL = 50 pF; -40 °C to +85 °C 7
clock pulse width HIGH or LOW tW 100 ns CP input HIGH or LOW; see Fig. 6; VCC = 2.0 V; -40 °C to +85 °C 7
clock pulse width HIGH or LOW tW 20 ns CP input HIGH or LOW; see Fig. 6; VCC = 4.5 V; -40 °C to +85 °C 7
clock pulse width HIGH or LOW tW 17 ns CP input HIGH or LOW; see Fig. 6; VCC = 6.0 V; -40 °C to +85 °C 7
set-up time Dn to CP tsu 75 ns Dn to CP; see Fig. 7; VCC = 2.0 V; -40 °C to +85 °C 7
set-up time Dn to CP tsu 15 ns Dn to CP; see Fig. 7; VCC = 4.5 V; -40 °C to +85 °C 7
set-up time Dn to CP tsu 13 ns Dn to CP; see Fig. 7; VCC = 6.0 V; -40 °C to +85 °C 7
set-up time E to CP tsu 75 ns E to CP; see Fig. 7; VCC = 2.0 V; -40 °C to +85 °C 7
set-up time E to CP tsu 15 ns E to CP; see Fig. 7; VCC = 4.5 V; -40 °C to +85 °C 7
set-up time E to CP tsu 13 ns E to CP; see Fig. 7; VCC = 6.0 V; -40 °C to +85 °C 7
hold time Dn to CP th 3 ns Dn to CP; see Fig. 7; VCC = 2.0 V; -40 °C to +85 °C 7
hold time E to CP th 4 ns E to CP; see Fig. 7; VCC = 2.0 V; -40 °C to +85 °C 7
maximum clock frequency fmax 5 MHz CP input; see Fig. 6; VCC = 2.0 V; -40 °C to +85 °C 7
maximum clock frequency fmax 24 MHz CP input; see Fig. 6; VCC = 4.5 V; -40 °C to +85 °C 7
maximum clock frequency fmax 28 MHz CP input; see Fig. 6; VCC = 6.0 V; -40 °C to +85 °C 7

CAD (KiCad official)

  • Symbol: 74HC377D
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: 74hc377d-etched.step / 74hc377d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc377d.step / 74hc377d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 d3e6848eadc38fcc, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF