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74HC166PW

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Nexperia Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC166PW

Nexperia · Shift Registers · TSSOP-16

74HC166PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DS input Serial data input; data enters the register serially at DS on each LOW-to-HIGH CP transition when PE is HIGH.
2 D0 input Parallel data input D0, loaded into the register on the LOW-to-HIGH CP transition when PE is LOW.
3 D1 input Parallel data input D1, loaded into the register on the LOW-to-HIGH CP transition when PE is LOW.
4 D2 input Parallel data input D2, loaded into the register on the LOW-to-HIGH CP transition when PE is LOW.
5 D3 input Parallel data input D3, loaded into the register on the LOW-to-HIGH CP transition when PE is LOW.
6 CE input Clock enable input, active LOW; data shifts on LOW-to-HIGH CP transitions while CE is LOW, and a HIGH on CE disables the CP input.
7 CP input Clock input, LOW-to-HIGH edge-triggered; drives the parallel load and serial shift operations.
8 GND power_in Ground (0 V) reference for all voltages.
9 MR input Asynchronous master reset, active LOW; clears the register independently of the clock.
10 D4 input Parallel data input D4, loaded into the register on the LOW-to-HIGH CP transition when PE is LOW.
11 D5 input Parallel data input D5, loaded into the register on the LOW-to-HIGH CP transition when PE is LOW.
12 D6 input Parallel data input D6, loaded into the register on the LOW-to-HIGH CP transition when PE is LOW.
13 Q7 output Serial output from the last stage of the 8-bit shift register.
14 D7 input Parallel data input D7, loaded into the register on the LOW-to-HIGH CP transition when PE is LOW.
15 PE input Parallel enable input, active LOW; LOW loads D0 to D7 on the next CP LOW-to-HIGH transition and HIGH selects serial entry at DS.
16 VCC power_in Positive supply voltage; recommended 2.0 V to 6.0 V for 74HC166 and 4.5 V to 5.5 V for 74HCT166.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply voltage VCC -0.5 7 V 6
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V [1] 6
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V [1] 6
Output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 6
Supply current ICC 50 mA 6
Ground current IGND -50 mA 6
Storage temperature Tstg -65 150 °C 6
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C [2] 6
Supply voltage 74HC166 VCC 2 5 6 V 6
Input voltage VI 0 V 6
Output voltage VO 0 V 6
Ambient temperature Tamb -40 125 °C 6
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 6
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 6
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 6
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V; -40 °C to +125 °C 6
HIGH-level input voltage VIH 3.15 V VCC = 4.5 V; -40 °C to +125 °C 6
HIGH-level input voltage VIH 4.2 V VCC = 6.0 V; -40 °C to +125 °C 6
LOW-level input voltage VIL 0.5 V VCC = 2.0 V; -40 °C to +125 °C 6
LOW-level input voltage VIL 1.35 V VCC = 4.5 V; -40 °C to +125 °C 6
LOW-level input voltage VIL 1.8 V VCC = 6.0 V; -40 °C to +125 °C 6
HIGH-level output voltage VOH 1.9 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 5.9 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 5.2 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; -40 °C to +125 °C 7
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C 7
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C 7
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C 7
Supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C 7
CP to Q7 propagation delay tpd 225 ns CP to Q7; see Fig. 8; VCC = 2.0 V; CL = 50 pF; -40 °C to +125 °C 8
CP to Q7 propagation delay tpd 45 ns CP to Q7; see Fig. 8; VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C 8
CP to Q7 propagation delay tpd 38 ns CP to Q7; see Fig. 8; VCC = 6.0 V; CL = 50 pF; -40 °C to +125 °C 8
MR to Q7 propagation delay tpd 240 ns MR to Q7; see Fig. 9; VCC = 2.0 V; CL = 50 pF; -40 °C to +125 °C 8
MR to Q7 propagation delay tpd 48 ns MR to Q7; see Fig. 9; VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C 8
MR to Q7 propagation delay tpd 41 ns MR to Q7; see Fig. 9; VCC = 6.0 V; CL = 50 pF; -40 °C to +125 °C 8
Output transition time tt 110 ns Output; see Fig. 8; VCC = 2.0 V; CL = 50 pF; -40 °C to +125 °C 8
Output transition time tt 22 ns Output; see Fig. 8; VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C 8
Output transition time tt 19 ns Output; see Fig. 8; VCC = 6.0 V; CL = 50 pF; -40 °C to +125 °C 8
CP pulse width HIGH or LOW tW 120 ns CP input HIGH or LOW; see Fig. 8; VCC = 2.0 V; -40 °C to +125 °C 8
CP pulse width HIGH or LOW tW 24 ns CP input HIGH or LOW; see Fig. 8; VCC = 4.5 V; -40 °C to +125 °C 8
CP pulse width HIGH or LOW tW 20 ns CP input HIGH or LOW; see Fig. 8; VCC = 6.0 V; -40 °C to +125 °C 8
MR pulse width LOW tW 150 ns MR input LOW; see Fig. 9; VCC = 2.0 V; -40 °C to +125 °C 8
MR pulse width LOW tW 30 ns MR input LOW; see Fig. 9; VCC = 4.5 V; -40 °C to +125 °C 8
MR pulse width LOW tW 26 ns MR input LOW; see Fig. 9; VCC = 6.0 V; -40 °C to +125 °C 8
Set-up time Dn, CE to CP tsu 120 ns Dn, CE to CP; see Fig. 10; VCC = 2.0 V; -40 °C to +125 °C 8
Set-up time Dn, CE to CP tsu 24 ns Dn, CE to CP; see Fig. 10; VCC = 4.5 V; -40 °C to +125 °C 8
Set-up time Dn, CE to CP tsu 20 ns Dn, CE to CP; see Fig. 10; VCC = 6.0 V; -40 °C to +125 °C 8
Set-up time PE to CP tsu 150 ns PE to CP; see Fig. 10; VCC = 2.0 V; -40 °C to +125 °C 8
Set-up time PE to CP tsu 30 ns PE to CP; see Fig. 10; VCC = 4.5 V; -40 °C to +125 °C 8
Set-up time PE to CP tsu 26 ns PE to CP; see Fig. 10; VCC = 6.0 V; -40 °C to +125 °C 8
Hold time PE to CP th 0 ns PE to CP; see Fig. 10; VCC = 2.0 V; -40 °C to +125 °C 9
Maximum frequency CP input fmax 4 MHz CP input; see Fig. 8; VCC = 2.0 V; -40 °C to +125 °C 9
Maximum frequency CP input fmax 20 MHz CP input; see Fig. 8; VCC = 4.5 V; -40 °C to +125 °C 9
Maximum frequency CP input fmax 24 MHz CP input; see Fig. 8; VCC = 6.0 V; -40 °C to +125 °C 9

CAD (KiCad official)

  • Symbol: 74HC166PW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc166pw-etched.step / 74hc166pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc166pw.step / 74hc166pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (17 pp, sha256 eaa7369d88204bc2, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF