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Name	Last commit message	Last updated
docs	74hc161m: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
viewers	74hc161m: viewers · Ray	1mo ago
74hc161m-etched.fit.json	74hc161m: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
74hc161m-etched.glb	74hc161m: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
74hc161m-etched.step	74hc161m: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
74hc161m.glb	Publish 0.1.0 · Ray	1mo ago
74hc161m.kicad_mod	Publish 0.1.0 · Ray	1mo ago
74hc161m.kicad_sym	Publish 0.1.0 · Ray	1mo ago
74hc161m.lbr	Publish 0.1.0 · Ray	1mo ago
74hc161m.step	Publish 0.1.0 · Ray	1mo ago
package.json	Publish 0.1.0 · Ray	1mo ago
page.json	74hc161m: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	27d ago
README.md	74hc161m: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	1mo ago

74HC161M

HGSEMI · Counters, Dividers · SOP-16

74HC161M from HGSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MR	input	Asynchronous master reset (active LOW). Driving MR LOW forces Q0-Q3 LOW regardless of the state of CP, PE, CET and CEP.
2	CP	input	Clock input, positive-edge triggered (LOW-to-HIGH transition). All internal flip-flops are clocked simultaneously on the rising edge.
3	D0	input	Parallel data input bit 0. Loaded into Q0 on the rising edge of CP when PE is LOW.
4	D1	input	Parallel data input bit 1. Loaded into Q1 on the rising edge of CP when PE is LOW.
5	D2	input	Parallel data input bit 2. Loaded into Q2 on the rising edge of CP when PE is LOW.
6	D3	input	Parallel data input bit 3. Loaded into Q3 on the rising edge of CP when PE is LOW.
7	CEP	input	Count enable input (active HIGH). Both CEP and CET must be HIGH to enable counting.
8	GND	power_in	Ground reference, 0 V.
9	PE	input	Parallel enable input (active LOW). When PE is LOW, D0-D3 are loaded into Q0-Q3 on the next rising edge of CP, disabling the counting action.
10	CET	input	Count enable carry input (active HIGH). Fed forward to enable the terminal count output (TC); both CEP and CET must be HIGH to count.
11	Q3	output	Flip-flop output bit 3 (MSB) of the 4-bit counter.
12	Q2	output	Flip-flop output bit 2 of the 4-bit counter.
13	Q1	output	Flip-flop output bit 1 of the 4-bit counter.
14	Q0	output	Flip-flop output bit 0 (LSB) of the 4-bit counter.
15	TC	output	Terminal count output. Goes HIGH when CET is HIGH and the counter reaches terminal count (HHHH = 15); produces a HIGH pulse approximately equal in duration to a HIGH output of Q0, used to enable the next cascaded stage.
16	VCC	power_in	Positive supply voltage, 2.0 V to 6.0 V (5.0 V typical).

Key specifications

Parameter	Value
Manufacturer	HGSEMI
Package	SOP-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

74HC161MM/TR
74HC161MMT/TR
74HC161MMS/TR

CAD (KiCad official)

Symbol: 74HC161M
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)
3D model files: 74hc161m-etched.step / 74hc161m-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc161m.step / 74hc161m.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HGSEMI datasheet (15 pp, sha256 1cbf2beb03386af9, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF