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74HC03N

Public Made by Adom

by adom

HGSEMI Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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74HC03N

HGSEMI · Logic Gates · DIP-14

74HC03N from HGSEMI, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of NAND gate channel 1; standard CMOS input that needs fast edge rates to avoid excess current and oscillation.
2 1B input Input B of NAND gate channel 1; standard CMOS input that needs fast edge rates to avoid excess current and oscillation.
3 1Y output Open-drain output of NAND gate channel 1; it can sink current to GND but not source current from VCC, so an external pull-up sets the high level.
4 2A input Input A of NAND gate channel 2; standard CMOS input that needs fast edge rates to avoid excess current and oscillation.
5 2B input Input B of NAND gate channel 2; standard CMOS input that needs fast edge rates to avoid excess current and oscillation.
6 2Y output Open-drain output of NAND gate channel 2; it can sink current to GND but not source current from VCC, so an external pull-up sets the high level.
7 GND power_in Ground reference for the device.
8 3Y output Open-drain output of NAND gate channel 3; it can sink current to GND but not source current from VCC, so an external pull-up sets the high level.
9 3A input Input A of NAND gate channel 3; standard CMOS input that needs fast edge rates to avoid excess current and oscillation.
10 3B input Input B of NAND gate channel 3; standard CMOS input that needs fast edge rates to avoid excess current and oscillation.
11 4Y output Open-drain output of NAND gate channel 4; it can sink current to GND but not source current from VCC, so an external pull-up sets the high level.
12 4A input Input A of NAND gate channel 4; standard CMOS input that needs fast edge rates to avoid excess current and oscillation.
13 4B input Input B of NAND gate channel 4; standard CMOS input that needs fast edge rates to avoid excess current and oscillation.
14 VCC power_in Positive supply; the recommended supply range is 2 V to 6 V with 5 V nominal.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2 5 6 V 3
Supply voltage VCC -0.5 7 V 3
High-level input voltage VIH 1.5 V VCC = 2 V 3
High-level input voltage VIH 3.15 V VCC = 4.5 V 3
High-level input voltage VIH 4.2 V VCC = 6 V 3
Low-level input voltage VIL 0.5 V VCC = 2 V 3
Low-level input voltage VIL 1.35 V VCC = 4.5 V 3
Low-level input voltage VIL 1.8 V VCC = 6 V 3
Input voltage VI 0 V maximum printed as VCC 3
Output voltage VO 0 V maximum printed as VCC 3
Input transition rise and fall rate Δt/Δv 1000 ns VCC = 2 V 3
Input transition rise and fall rate Δt/Δv 500 ns VCC = 4.5 V 3
Input transition rise and fall rate Δt/Δv 400 ns VCC = 6 V 3
Operating free-air temperature TA -40 85 °C 74HC03 3
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 3
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 3
Continuous output current IO -25 25 mA VO = 0 to VCC 3
Continuous current through VCC or GND -50 50 mA 3
Junction temperature TJ 150 °C 3
Storage temperature Tstg -65 150 °C 3
Lead temperature (soldering) TL 245 °C Soldering, 10 seconds 3
Output voltage (open-drain off state) IOH 0.01 0.5 µA VI = VIH or VIL, VO = VCC, VCC 6 V, TA 25°C 4
Output voltage (open-drain off state) IOH 5 µA VI = VIH or VIL, VO = VCC, VCC 6 V, TA -40°C to 85°C 4
Low-level output voltage VOL 0.002 0.1 V VI = VIH or VIL, IOL = 20 µA, VCC 2 V, TA 25°C 4
Low-level output voltage VOL 0.1 V VI = VIH or VIL, IOL = 20 µA, VCC 2 V, TA -40°C to 85°C 4
Low-level output voltage VOL 0.001 0.1 V VI = VIH or VIL, IOL = 20 µA, VCC 4.5 V, TA 25°C 4
Low-level output voltage VOL 0.17 0.26 V VI = VIH or VIL, IOL = 4 mA, VCC 4.5 V, TA 25°C 4
Low-level output voltage VOL 0.33 V VI = VIH or VIL, IOL = 4 mA, VCC 4.5 V, TA -40°C to 85°C 4
Low-level output voltage VOL 0.15 0.26 V VI = VIH or VIL, IOL = 5.2 mA, VCC 6 V, TA 25°C 4
Input leakage current II -1 0.1 1 µA VI = VCC or 0, VCC 6 V 4
Supply current ICC 2 20 µA VI = VCC or 0, IO = 0, VCC 6 V 4
Input capacitance Ci 3 10 pF VCC 2 V to 6 V 4
Propagation delay, low-to-high tPLH 60 105 ns A or B to Y, VCC 2 V, TA 25°C 5
Propagation delay, low-to-high tPLH 131 ns A or B to Y, VCC 2 V, TA -40°C to 85°C 5
Propagation delay, low-to-high tPLH 13 25 ns A or B to Y, VCC 4.5 V, TA 25°C 5
Propagation delay, low-to-high tPLH 31 ns A or B to Y, VCC 4.5 V, TA -40°C to 85°C 5
Propagation delay, low-to-high tPLH 10 23 ns A or B to Y, VCC 6 V, TA 25°C 5
Propagation delay, low-to-high tPLH 27 ns A or B to Y, VCC 6 V, TA -40°C to 85°C 5
Propagation delay, high-to-low tPHL 50 100 ns A or B to Y, VCC 2 V, TA 25°C 5
Propagation delay, high-to-low tPHL 125 ns A or B to Y, VCC 2 V, TA -40°C to 85°C 5
Propagation delay, high-to-low tPHL 10 20 ns A or B to Y, VCC 4.5 V, TA 25°C 5
Propagation delay, high-to-low tPHL 25 ns A or B to Y, VCC 4.5 V, TA -40°C to 85°C 5
Propagation delay, high-to-low tPHL 8 17 ns A or B to Y, VCC 6 V, TA 25°C 5
Propagation delay, high-to-low tPHL 21 ns A or B to Y, VCC 6 V, TA -40°C to 85°C 5
Transition time tt 38 75 ns Y, VCC 2 V, TA 25°C 5
Transition time tt 95 ns Y, VCC 2 V, TA -40°C to 85°C 5
Transition time tt 8 15 ns Y, VCC 4.5 V, TA 25°C 5
Transition time tt 19 ns Y, VCC 4.5 V, TA -40°C to 85°C 5
Transition time tt 6 13 ns Y, VCC 6 V, TA 25°C 5
Transition time tt 16 ns Y, VCC 6 V, TA -40°C to 85°C 5
Junction-to-ambient thermal resistance (DIP) RθJA 66 °C/W DIP-14 4
Junction-to-case (top) thermal resistance (DIP) RθJC(top) 53.7 °C/W DIP-14 4
Junction-to-board thermal resistance (DIP) RθJB 45.7 °C/W DIP-14 4

CAD (KiCad official)

  • Symbol: 74HC03N
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: 74hc03n-etched.step / 74hc03n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc03n.step / 74hc03n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (12 pp, sha256 3cd6c9e16e4bdd1d, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF