74HC00D

{
  "slug": "74hc00d",
  "version": "0.2.1",
  "type": "component",
  "description": "Nexperia Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "74hc00d"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "74hc00d.kicad_sym",
    "74hc00d.kicad_mod",
    "74hc00d.glb",
    "74hc00d.step",
    "74hc00d-etched.step",
    "74hc00d.lbr",
    "docs/hero.png",
    "docs/74hc00d-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "pads.json",
    "74hc00d-hero.glb",
    "74hc00d-hero.overlay.json"
  ],
  "component": {
    "mpn": "74HC00D",
    "manufacturer": "Nexperia",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Gates",
    "datasheet": "https://assets.nexperia.com/documents/data-sheet/74HC00D.pdf",
    "parts": {
      "symbol": "74hc00d.kicad_sym",
      "footprint": "74hc00d.kicad_mod",
      "model_3d": "74hc00d-hero.glb",
      "model_3d_plain": "74hc00d.glb",
      "model_3d_step": "74hc00d-etched.step",
      "model_3d_step_plain": "74hc00d.step",
      "lbr": "74hc00d.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Gate 1 data input A. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 1B in a 2-input NAND to produce 1Y."
      },
      {
        "number": "2",
        "name": "1B",
        "type": "input",
        "description": "Gate 1 data input B. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 1A in a 2-input NAND to produce 1Y."
      },
      {
        "number": "3",
        "name": "1Y",
        "type": "output",
        "description": "Gate 1 data output. Push-pull CMOS output: 1Y = NAND(1A, 1B). Drives up to ±5.2 mA at VCC = 6.0 V."
      },
      {
        "number": "4",
        "name": "2A",
        "type": "input",
        "description": "Gate 2 data input A. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 2B in a 2-input NAND to produce 2Y."
      },
      {
        "number": "5",
        "name": "2B",
        "type": "input",
        "description": "Gate 2 data input B. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 2A in a 2-input NAND to produce 2Y."
      },
      {
        "number": "6",
        "name": "2Y",
        "type": "output",
        "description": "Gate 2 data output. Push-pull CMOS output: 2Y = NAND(2A, 2B). Drives up to ±5.2 mA at VCC = 6.0 V."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V). All voltages in the datasheet are referenced to this pin."
      },
      {
        "number": "8",
        "name": "3Y",
        "type": "output",
        "description": "Gate 3 data output. Push-pull CMOS output: 3Y = NAND(3A, 3B). Drives up to ±5.2 mA at VCC = 6.0 V."
      },
      {
        "number": "9",
        "name": "3A",
        "type": "input",
        "description": "Gate 3 data input A. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 3B in a 2-input NAND to produce 3Y."
      },
      {
        "number": "10",
        "name": "3B",
        "type": "input",
        "description": "Gate 3 data input B. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 3A in a 2-input NAND to produce 3Y."
      },
      {
        "number": "11",
        "name": "4Y",
        "type": "output",
        "description": "Gate 4 data output. Push-pull CMOS output: 4Y = NAND(4A, 4B). Drives up to ±5.2 mA at VCC = 6.0 V."
      },
      {
        "number": "12",
        "name": "4A",
        "type": "input",
        "description": "Gate 4 data input A. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 4B in a 2-input NAND to produce 4Y."
      },
      {
        "number": "13",
        "name": "4B",
        "type": "input",
        "description": "Gate 4 data input B. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 4A in a 2-input NAND to produce 4Y."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage. Operating range 2.0 V to 6.0 V for 74HC00 (4.5 V to 5.5 V for 74HCT00). Decouple to GND with a 100 nF ceramic capacitor placed close to the pin."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://assets.nexperia.com/documents/data-sheet/74HC00D.pdf",
        "pages": 12,
        "sha256": "a01759669120aa7d",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -3.81
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-14_3.9x8.7mm_P1.27mm@sha256:a885b619b22880c9",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "74HC00",
      "logic_family": "74HC",
      "function_code": "00",
      "function_class": "Gate",
      "function_name": "Quad 2-Input NAND Gate",
      "manufacturer": null,
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "74hc00d.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "74hc00d-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "e4a77e4b076d8720b76eb2b49a0db1a74929a16b2a248c3a39481f3df334c970",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "title": "74HC00D",
  "brief": "Nexperia Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "metadata": {
    "specs": {
      "Manufacturer": "Nexperia",
      "Package": "SOIC-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "discovery_triggers": [
    "74hc00d"
  ],
  "discovery_pitch": "74HC00D (Nexperia) component page with datasheet-verified CAD.",
  "visibility": "public"
}