component

74HC00D

Public Made by Adom

by adom

Nexperia Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs 74hc00d: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
74hc00d-etched.fit.json 74hc00d: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
74hc00d-etched.glb 74hc00d: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body wit… · Ray
74hc00d-etched.step 74hc00d: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body wit… · Ray
74hc00d-hero.glb 74hc00d: hero from the plain model · Ray
74hc00d-hero.overlay.json 74hc00d: hero from the plain model · Ray
74hc00d.glb Publish 0.1.0 · Ray
74hc00d.kicad_mod Publish 0.1.0 · Ray
74hc00d.kicad_sym Publish 0.1.0 · Ray
74hc00d.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
74hc00d.step Publish 0.1.0 · Ray
package.json Publish 0.2.1 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json Publish 0.2.1 · Ray
README.md 74hc00d: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

74HC00D

Nexperia · Gates · SOIC-14

74HC00D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 data input A. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 1B in a 2-input NAND to produce 1Y.
2 1B input Gate 1 data input B. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 1A in a 2-input NAND to produce 1Y.
3 1Y output Gate 1 data output. Push-pull CMOS output: 1Y = NAND(1A, 1B). Drives up to ±5.2 mA at VCC = 6.0 V.
4 2A input Gate 2 data input A. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 2B in a 2-input NAND to produce 2Y.
5 2B input Gate 2 data input B. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 2A in a 2-input NAND to produce 2Y.
6 2Y output Gate 2 data output. Push-pull CMOS output: 2Y = NAND(2A, 2B). Drives up to ±5.2 mA at VCC = 6.0 V.
7 GND power_in Ground reference (0 V). All voltages in the datasheet are referenced to this pin.
8 3Y output Gate 3 data output. Push-pull CMOS output: 3Y = NAND(3A, 3B). Drives up to ±5.2 mA at VCC = 6.0 V.
9 3A input Gate 3 data input A. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 3B in a 2-input NAND to produce 3Y.
10 3B input Gate 3 data input B. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 3A in a 2-input NAND to produce 3Y.
11 4Y output Gate 4 data output. Push-pull CMOS output: 4Y = NAND(4A, 4B). Drives up to ±5.2 mA at VCC = 6.0 V.
12 4A input Gate 4 data input A. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 4B in a 2-input NAND to produce 4Y.
13 4B input Gate 4 data input B. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 4A in a 2-input NAND to produce 4Y.
14 VCC power_in Positive supply voltage. Operating range 2.0 V to 6.0 V for 74HC00 (4.5 V to 5.5 V for 74HCT00). Decouple to GND with a 100 nF ceramic capacitor placed close to the pin.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-14
Category Logic
Pins 14

Ordering variants

  • 74HC00DD
  • 74HC00DPW
  • 74HC00DBQ

CAD (KiCad official)

  • Symbol: 74HC00D
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: 74hc00d-etched.step / 74hc00d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc00d.step / 74hc00d.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
74hc00d.step 195 KB You want the bare part, or you mark your own boards.
74hc00d-etched.step 1.8 MB You want the part with 74HC00D already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 466 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (12 pp, sha256 a01759669120aa7d, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF