74AHCT595T16-13

{
  "slug": "74ahct595t16-13",
  "version": "0.1.0",
  "type": "component",
  "description": "Diodes Incorporated Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "logic",
    "74ahct595t16-13",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
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    "74ahct595t16-13.step",
    "74ahct595t16-13.lbr",
    "docs/hero.png",
    "docs/74ahct595t16-13-datasheet.pdf",
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  "component": {
    "mpn": "74AHCT595T16-13",
    "manufacturer": "Diodes Incorporated",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shift Registers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588935989327253504",
    "parts": {
      "symbol": "74ahct595t16-13.kicad_sym",
      "footprint": "74ahct595t16-13.kicad_mod",
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      "model_3d_plain": "74ahct595t16-13.glb",
      "model_3d_step": "74ahct595t16-13-etched.step",
      "model_3d_step_plain": "74ahct595t16-13.step",
      "lbr": "74ahct595t16-13.lbr"
    },
    "distributor_links": {
      "lcsc": "C460504",
      "digikey": "31-74AHCT595T16-13TR-ND",
      "mouser": "621-74AHCT595T16-13"
    },
    "distributor_check": {
      "checked_at": "2026-10-09T20:17:09Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "31-74AHCT595T16-13TR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "621-74AHCT595T16-13",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "Q1",
        "type": "tri_state",
        "description": "Parallel data output 1 is a 3-state output that becomes active when OE is asserted low and goes to high impedance when OE is high."
      },
      {
        "number": "2",
        "name": "Q2",
        "type": "tri_state",
        "description": "Parallel data output 2 is a 3-state output that becomes active when OE is asserted low and goes to high impedance when OE is high."
      },
      {
        "number": "3",
        "name": "Q3",
        "type": "tri_state",
        "description": "Parallel data output 3 is a 3-state output that becomes active when OE is asserted low and goes to high impedance when OE is high."
      },
      {
        "number": "4",
        "name": "Q4",
        "type": "tri_state",
        "description": "Parallel data output 4 is a 3-state output that becomes active when OE is asserted low and goes to high impedance when OE is high."
      },
      {
        "number": "5",
        "name": "Q5",
        "type": "tri_state",
        "description": "Parallel data output 5 is a 3-state output that becomes active when OE is asserted low and goes to high impedance when OE is high."
      },
      {
        "number": "6",
        "name": "Q6",
        "type": "tri_state",
        "description": "Parallel data output 6 is a 3-state output that becomes active when OE is asserted low and goes to high impedance when OE is high."
      },
      {
        "number": "7",
        "name": "Q7",
        "type": "tri_state",
        "description": "Parallel data output 7 is a 3-state output that becomes active when OE is asserted low and goes to high impedance when OE is high."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference pin for the device."
      },
      {
        "number": "9",
        "name": "Q7S",
        "type": "output",
        "description": "Serial data output carries the contents of the last shift register stage (Q6S shifted to Q7S) and is not affected by OE or MR."
      },
      {
        "number": "10",
        "name": "MR",
        "type": "input",
        "description": "Active-low master reset input that clears the shift register to zero independently of the clocks when asserted low."
      },
      {
        "number": "11",
        "name": "SHCP",
        "type": "input",
        "description": "Shift register clock input; data on DS is shifted into the first stage on each rising edge."
      },
      {
        "number": "12",
        "name": "STCP",
        "type": "input",
        "description": "Storage register clock input; a rising edge transfers the shift register contents into the storage (output) register."
      },
      {
        "number": "13",
        "name": "OE",
        "type": "input",
        "description": "Active-low output enable input; when held high the Q0-Q7 outputs are forced to the high-impedance state."
      },
      {
        "number": "14",
        "name": "DS",
        "type": "input",
        "description": "Serial data input; inputs accept up to 5.5 V with Schmitt-trigger action and data is captured on the rising edge of the shift clock."
      },
      {
        "number": "15",
        "name": "Q0",
        "type": "tri_state",
        "description": "Parallel data output 0 is a 3-state output that becomes active when OE is asserted low and goes to high impedance when OE is high."
      },
      {
        "number": "16",
        "name": "Vcc",
        "type": "power_in",
        "description": "Supply voltage pin; recommended operating range is 4.5 V to 5.5 V and absolute maximum is -0.5 V to +7.0 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet pin table is a single device-level table; it does not separately state a TSSOP-16 pin ; Datasheet is internally inconsistent on the clock names. The page 1 description says the serial inpu; Q7S description is a summary of the function table (page 3); the datasheet does not state its electr"
        ],
        "pages_sent": 10,
        "cost_usd": 0.06,
        "at": "2026-10-09T20:14:47"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588935989327253504",
        "pages": 10,
        "sha256": "4dc912eff08d0048",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
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        "checked": "2026-10-09",
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        "sha256": "f09d6622f47f2daa7314b46807176fd99a7415dfa0f3bb4d6b2acd29afbb1c49",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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}