74AHCT32PW-Q100J

{
  "schema_version": 1,
  "type": "component",
  "slug": "74ahct32pw-q100j",
  "title": "74AHCT32PW-Q100J",
  "brief": "Nexperia Logic Gates, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "74ahct32pw-q100j"
  ],
  "component": {
    "mpn": "74AHCT32PW-Q100J",
    "manufacturer": "Nexperia",
    "package": "TSSOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://assets.nexperia.com/documents/data-sheet/74AHCT32PW-Q100J.pdf",
    "parts": {
      "symbol": "74ahct32pw-q100j.kicad_sym",
      "footprint": "74ahct32pw-q100j.kicad_mod",
      "model_3d": "74ahct32pw-q100j-etched.glb",
      "model_3d_plain": "74ahct32pw-q100j.glb",
      "model_3d_step": "74ahct32pw-q100j-etched.step",
      "model_3d_step_plain": "74ahct32pw-q100j.step",
      "lbr": "74ahct32pw-q100j.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Gate 1 data input A. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V independent of VCC. V_IH ≥ 2.0 V, V_IL ≤ 0.8 V (VCC = 4.5-5.5 V)."
      },
      {
        "number": "2",
        "name": "1B",
        "type": "input",
        "description": "Gate 1 data input B. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V. V_IH ≥ 2.0 V, V_IL ≤ 0.8 V (VCC = 4.5-5.5 V)."
      },
      {
        "number": "3",
        "name": "1Y",
        "type": "output",
        "description": "Gate 1 OR output (1Y = 1A OR 1B). Push-pull CMOS output; V_OH ≥ 3.94 V and V_OL ≤ 0.36 V at ±8 mA drive with VCC = 4.5 V. Clamping current limited to ±20 mA."
      },
      {
        "number": "4",
        "name": "2A",
        "type": "input",
        "description": "Gate 2 data input A. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V."
      },
      {
        "number": "5",
        "name": "2B",
        "type": "input",
        "description": "Gate 2 data input B. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V."
      },
      {
        "number": "6",
        "name": "2Y",
        "type": "output",
        "description": "Gate 2 OR output (2Y = 2A OR 2B). Push-pull CMOS output; ±8 mA drive at VCC = 4.5 V."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground (0 V) reference for the device. All input and output voltages are referenced to this pin."
      },
      {
        "number": "8",
        "name": "3Y",
        "type": "output",
        "description": "Gate 3 OR output (3Y = 3A OR 3B). Push-pull CMOS output; ±8 mA drive at VCC = 4.5 V."
      },
      {
        "number": "9",
        "name": "3A",
        "type": "input",
        "description": "Gate 3 data input A. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V."
      },
      {
        "number": "10",
        "name": "3B",
        "type": "input",
        "description": "Gate 3 data input B. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V."
      },
      {
        "number": "11",
        "name": "4Y",
        "type": "output",
        "description": "Gate 4 OR output (4Y = 4A OR 4B). Push-pull CMOS output; ±8 mA drive at VCC = 4.5 V."
      },
      {
        "number": "12",
        "name": "4A",
        "type": "input",
        "description": "Gate 4 data input A. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V."
      },
      {
        "number": "13",
        "name": "4B",
        "type": "input",
        "description": "Gate 4 data input B. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage, 2.0 V to 5.5 V recommended (4.5 V to 5.5 V for guaranteed TTL-input timing). Absolute maximum 7.0 V. Bypass locally with a 100 nF ceramic capacitor."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://assets.nexperia.com/documents/data-sheet/74AHCT32PW-Q100J.pdf",
        "pages": 13,
        "sha256": "584eb7f5ed99cfbb",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74AHCT32",
      "logic_family": "74AHCT",
      "function_code": "32",
      "function_class": "Gate",
      "function_name": "Quad 2-Input OR Gate",
      "manufacturer": null,
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "74ahct32pw-q100j.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.0
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3ee5786aae56190997aa793ba3cfc003fd616782770e29719b4562f012982245",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "74ahct32pw-q100j-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.0
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "2bde060dd038b6e5687e0997d39ff786fd9a6f015563023dac4990242aebc353",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Nexperia",
      "Package": "TSSOP-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "variants": [
    {
      "mpn": "74AHCT32PW-Q100J",
      "kind": "packaging"
    },
    {
      "mpn": "74AHCT32PW-Q100JD-Q100",
      "kind": "packaging"
    },
    {
      "mpn": "74AHCT32PW-Q100JBQ-Q100",
      "kind": "packaging"
    }
  ],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "74ahct32pw-q100j"
  ],
  "discovery_pitch": "74AHCT32PW-Q100J (Nexperia) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "74ahct32pw-q100j.kicad_sym",
    "74ahct32pw-q100j.kicad_mod",
    "74ahct32pw-q100j.glb",
    "74ahct32pw-q100j.step",
    "74ahct32pw-q100j.lbr",
    "docs/hero.png",
    "docs/74ahct32pw-q100j-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T14:47:08.499Z"
}