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74AHCT32PW-Q100J

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Nexperia Logic Gates, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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docs 74ahct32pw-q100j: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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74ahct32pw-q100j-etched.fit.json 74ahct32pw-q100j: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74ahct32pw-q100j-etched.glb 74ahct32pw-q100j: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74ahct32pw-q100j-etched.step 74ahct32pw-q100j: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74ahct32pw-q100j.glb Publish 0.1.0 · Ray 1mo ago
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README.md 74ahct32pw-q100j: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

74AHCT32PW-Q100J

Nexperia · Logic Gates · TSSOP-14

74AHCT32PW-Q100J from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 data input A. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V independent of VCC. V_IH ≥ 2.0 V, V_IL ≤ 0.8 V (VCC = 4.5-5.5 V).
2 1B input Gate 1 data input B. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V. V_IH ≥ 2.0 V, V_IL ≤ 0.8 V (VCC = 4.5-5.5 V).
3 1Y output Gate 1 OR output (1Y = 1A OR 1B). Push-pull CMOS output; V_OH ≥ 3.94 V and V_OL ≤ 0.36 V at ±8 mA drive with VCC = 4.5 V. Clamping current limited to ±20 mA.
4 2A input Gate 2 data input A. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V.
5 2B input Gate 2 data input B. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V.
6 2Y output Gate 2 OR output (2Y = 2A OR 2B). Push-pull CMOS output; ±8 mA drive at VCC = 4.5 V.
7 GND power_in Ground (0 V) reference for the device. All input and output voltages are referenced to this pin.
8 3Y output Gate 3 OR output (3Y = 3A OR 3B). Push-pull CMOS output; ±8 mA drive at VCC = 4.5 V.
9 3A input Gate 3 data input A. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V.
10 3B input Gate 3 data input B. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V.
11 4Y output Gate 4 OR output (4Y = 4A OR 4B). Push-pull CMOS output; ±8 mA drive at VCC = 4.5 V.
12 4A input Gate 4 data input A. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V.
13 4B input Gate 4 data input B. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V.
14 VCC power_in Positive supply voltage, 2.0 V to 5.5 V recommended (4.5 V to 5.5 V for guaranteed TTL-input timing). Absolute maximum 7.0 V. Bypass locally with a 100 nF ceramic capacitor.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • 74AHCT32PW-Q100J
  • 74AHCT32PW-Q100JD-Q100
  • 74AHCT32PW-Q100JBQ-Q100

CAD (KiCad official)

  • Symbol: 74AHCT32PW-Q100J
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74ahct32pw-q100j-etched.step / 74ahct32pw-q100j-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74ahct32pw-q100j.step / 74ahct32pw-q100j.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (13 pp, sha256 584eb7f5ed99cfbb, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF