component
74ACT11008D
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
74act11008d: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body…
09f5afa
7d ago
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"description": "Texas Instruments Logic Gates, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"dependencies": {},
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"74act11008d.step",
"74act11008d.lbr",
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"viewers/symbol.html",
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"component": {
"mpn": "74ACT11008D",
"manufacturer": "Texas Instruments",
"package": "SOIC-16",
"pin_count": 16,
"category": "Logic",
"subcategory": "Logic Gates",
"datasheet": "https://www.ti.com/cn/lit/gpn/74act11008",
"parts": {
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"footprint": "74act11008d.kicad_mod",
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"model_3d_step_plain": "74act11008d.step",
"lbr": "74act11008d.lbr"
},
"distributor_links": {
"lcsc": "C2868328",
"digikey": "2156-74ACT11008D-ND",
"mouser": "595-74ACT11008D"
},
"distributor_check": {
"checked_at": "2026-10-11T17:12:31Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "2156-74ACT11008D-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "595-74ACT11008D",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "1A",
"type": "input",
"description": "Data input A of gate 1 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V."
},
{
"number": "2",
"name": "1Y",
"type": "output",
"description": "Output of gate 1, Y = A·B in positive logic."
},
{
"number": "3",
"name": "2Y",
"type": "output",
"description": "Output of gate 2, Y = A·B in positive logic."
},
{
"number": "4",
"name": "GND",
"type": "power_in",
"description": "Ground reference; one of two center-pin GND connections in the datasheet's center-pin VCC/GND configuration that minimizes high-speed switching noise."
},
{
"number": "5",
"name": "GND",
"type": "power_in",
"description": "Ground reference; second of two center-pin GND connections in the datasheet's center-pin VCC/GND configuration that minimizes high-speed switching noise."
},
{
"number": "6",
"name": "3Y",
"type": "output",
"description": "Output of gate 3, Y = A·B in positive logic."
},
{
"number": "7",
"name": "4Y",
"type": "output",
"description": "Output of gate 4, Y = A·B in positive logic."
},
{
"number": "8",
"name": "4B",
"type": "input",
"description": "Data input B of gate 4 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V."
},
{
"number": "9",
"name": "4A",
"type": "input",
"description": "Data input A of gate 4 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V."
},
{
"number": "10",
"name": "3B",
"type": "input",
"description": "Data input B of gate 3 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V."
},
{
"number": "11",
"name": "3A",
"type": "input",
"description": "Data input A of gate 3 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V."
},
{
"number": "12",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage, recommended 4.5 V to 5.5 V; one of two center-pin VCC connections."
},
{
"number": "13",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage, recommended 4.5 V to 5.5 V; second of two center-pin VCC connections."
},
{
"number": "14",
"name": "2B",
"type": "input",
"description": "Data input B of gate 2 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V."
},
{
"number": "15",
"name": "2A",
"type": "input",
"description": "Data input A of gate 2 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V."
},
{
"number": "16",
"name": "1B",
"type": "input",
"description": "Data input B of gate 1 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The TOP VIEW pin list on page 1 is scrambled in the extracted text. Pin assignments were reconstruct; The datasheet gives one TOP VIEW for the 'D, N, OR PW PACKAGE' and does not print a separate pinout ; Pins 12 and 13 (VCC) have their voltage limits on page 2, so their source_page is 2. The other pins "
],
"pages_sent": 13,
"cost_usd": 0.0565,
"at": "2026-10-11T17:12:15"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/74act11008",
"pages": 13,
"sha256": "cb63f8b8b17095e2",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
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"footprint": "viewers/footprint.html"
},
"models_3d": [
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"extents_mm": [
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"footprint_binding": "identity",
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"checked": "2026-10-11",
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},
{
"file": "74act11008d-etched.step",
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"checked": "2026-10-21",
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}
}