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74ACT11008D
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74ACT11008D
Texas Instruments · Logic Gates · SOIC-16
74ACT11008D from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input A of gate 1 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 2 | 1Y | output | Output of gate 1, Y = A·B in positive logic. |
| 3 | 2Y | output | Output of gate 2, Y = A·B in positive logic. |
| 4 | GND | power_in | Ground reference; one of two center-pin GND connections in the datasheet's center-pin VCC/GND configuration that minimizes high-speed switching noise. |
| 5 | GND | power_in | Ground reference; second of two center-pin GND connections in the datasheet's center-pin VCC/GND configuration that minimizes high-speed switching noise. |
| 6 | 3Y | output | Output of gate 3, Y = A·B in positive logic. |
| 7 | 4Y | output | Output of gate 4, Y = A·B in positive logic. |
| 8 | 4B | input | Data input B of gate 4 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 9 | 4A | input | Data input A of gate 4 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 10 | 3B | input | Data input B of gate 3 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 11 | 3A | input | Data input A of gate 3 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 12 | VCC | power_in | Supply voltage, recommended 4.5 V to 5.5 V; one of two center-pin VCC connections. |
| 13 | VCC | power_in | Supply voltage, recommended 4.5 V to 5.5 V; second of two center-pin VCC connections. |
| 14 | 2B | input | Data input B of gate 2 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 15 | 2A | input | Data input A of gate 2 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 16 | 1B | input | Data input B of gate 1 of the 2-input AND gate (Y = AB); input is TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
74ACT11008D - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
74act11008d-etched.step/74act11008d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74act11008d.step/74act11008d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (13 pp, sha256
cb63f8b8b17095e2, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).