74ACT08MTC

{
  "schema_version": 1,
  "type": "component",
  "slug": "74act08mtc",
  "title": "74ACT08MTC",
  "brief": "onsemi Logic Gates, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "74act08mtc"
  ],
  "component": {
    "mpn": "74ACT08MTC",
    "manufacturer": "onsemi",
    "package": "TSSOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589997703792271361",
    "parts": {
      "symbol": "74act08mtc.kicad_sym",
      "footprint": "74act08mtc.kicad_mod",
      "model_3d": "74act08mtc-etched.glb",
      "model_3d_plain": "74act08mtc.glb",
      "model_3d_step": "74act08mtc-etched.step",
      "model_3d_step_plain": "74act08mtc.step",
      "lbr": "74act08mtc.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "A0",
        "type": "input",
        "description": "Input A of gate 0 (first 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."
      },
      {
        "number": "2",
        "name": "B0",
        "type": "input",
        "description": "Input B of gate 0 (first 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."
      },
      {
        "number": "3",
        "name": "O0",
        "type": "output",
        "description": "Output of gate 0 = A0 AND B0. Push-pull CMOS output sourcing/sinking 24 mA (VOH ≥ 3.76V @ IOH=-24mA, VOL ≤ 0.44V @ IOL=24mA at VCC=4.5V)."
      },
      {
        "number": "4",
        "name": "A1",
        "type": "input",
        "description": "Input A of gate 1 (second 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."
      },
      {
        "number": "5",
        "name": "B1",
        "type": "input",
        "description": "Input B of gate 1 (second 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."
      },
      {
        "number": "6",
        "name": "O1",
        "type": "output",
        "description": "Output of gate 1 = A1 AND B1. Push-pull CMOS output sourcing/sinking 24 mA (VOH ≥ 3.76V @ IOH=-24mA, VOL ≤ 0.44V @ IOL=24mA at VCC=4.5V)."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0V). Common ground return for all four gates."
      },
      {
        "number": "8",
        "name": "O3",
        "type": "output",
        "description": "Output of gate 3 = A3 AND B3. Push-pull CMOS output sourcing/sinking 24 mA (VOH ≥ 3.76V @ IOH=-24mA, VOL ≤ 0.44V @ IOL=24mA at VCC=4.5V)."
      },
      {
        "number": "9",
        "name": "B3",
        "type": "input",
        "description": "Input B of gate 3 (fourth 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."
      },
      {
        "number": "10",
        "name": "A3",
        "type": "input",
        "description": "Input A of gate 3 (fourth 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."
      },
      {
        "number": "11",
        "name": "O2",
        "type": "output",
        "description": "Output of gate 2 = A2 AND B2. Push-pull CMOS output sourcing/sinking 24 mA (VOH ≥ 3.76V @ IOH=-24mA, VOL ≤ 0.44V @ IOL=24mA at VCC=4.5V)."
      },
      {
        "number": "12",
        "name": "B2",
        "type": "input",
        "description": "Input B of gate 2 (third 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."
      },
      {
        "number": "13",
        "name": "A2",
        "type": "input",
        "description": "Input A of gate 2 (third 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage. Recommended operating range 4.5V to 5.5V for 74ACT08 (TTL-compatible thresholds). Absolute maximum -0.5V to +7.0V."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589997703792271361",
        "pages": 7,
        "sha256": "d37456fb09b16dc7",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74ACT08",
      "logic_family": "74ACT",
      "function_code": "08",
      "function_class": "Gate",
      "function_name": "Quad 2-Input AND Gate",
      "manufacturer": null,
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "74act08mtc.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.0
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3ee5786aae56190997aa793ba3cfc003fd616782770e29719b4562f012982245",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "74act08mtc-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.0
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "5c269cd24a8527756735c6a694329d8d806fdaa7caf1a28f93d1dfe04cc31cd9",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "onsemi",
      "Package": "TSSOP-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "variants": [
    {
      "mpn": "74ACT08MTC",
      "kind": "packaging"
    },
    {
      "mpn": "74ACT08MTCX",
      "kind": "packaging"
    },
    {
      "mpn": "74ACT08MTCSC",
      "kind": "packaging"
    },
    {
      "mpn": "74ACT08MTCSCX",
      "kind": "packaging"
    },
    {
      "mpn": "74ACT08MTCPC",
      "kind": "packaging"
    }
  ],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "74act08mtc"
  ],
  "discovery_pitch": "74ACT08MTC (onsemi) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "74act08mtc.kicad_sym",
    "74act08mtc.kicad_mod",
    "74act08mtc.glb",
    "74act08mtc.step",
    "74act08mtc.lbr",
    "docs/hero.png",
    "docs/74act08mtc-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T14:43:27.757Z"
}