# 4884

**HL** · MOSFETs · SOP-8

4884 from HL, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of N-channel MOSFET 1. |
| 2 | G1 | input | Gate of N-channel MOSFET 1; gate-source voltage limited to ±20 V. |
| 3 | S2 | passive | Source of N-channel MOSFET 2. |
| 4 | G2 | input | Gate of N-channel MOSFET 2; gate-source voltage limited to ±20 V. |
| 5 | D2 | passive | Drain of N-channel MOSFET 2; drain-source voltage rated 40 V. |
| 6 | D2 | passive | Drain of N-channel MOSFET 2, internally tied to pin 5; drain-source voltage rated 40 V. |
| 7 | D1 | passive | Drain of N-channel MOSFET 1; drain-source voltage rated 40 V. |
| 8 | D1 | passive | Drain of N-channel MOSFET 1, internally tied to pin 7; drain-source voltage rated 40 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HL |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS |  |  | 40 | V |  | 1 |
| Gate-Source Voltage | VGS |  |  | 20 | V |  | 1 |
| Continuous Drain Current | ID |  |  | 12 | A | @T=25℃ | 1 |
| Continuous Drain Current | ID |  |  | 7 | A | @T=100℃ | 1 |
| Pulsed Drain Current | IDM |  |  | 40 | A |  | 1 |
| Single Pulse Avalanche Energy | EAS |  |  | 31 | mJ |  | 1 |
| Avalanche Current | IAS |  |  | 10 | A |  | 1 |
| Total Power Dissipation | PD |  |  | 2.9 | W | @T=25℃ | 1 |
| Storage Temperature Range | TSTG | -55 |  | 150 | ℃ |  | 1 |
| Operating Junction Temperature Range | TJ | -55 |  | 150 | ℃ |  | 1 |
| Thermal Resistance Junction-ambient (t≤10s) | RθJA |  |  | 40 | ℃/W | t≤10s | 1 |
| Thermal Resistance Junction-ambient | RθJA |  |  | 65 | ℃/W |  | 1 |
| Drain-Source Breakdown Voltage | BVDSS | 40 |  |  | V | VGS=0V, ID=250μA | 2 |
| Zero Gate Voltage Drain Current | IDSS |  |  | 1 | μA | VDS=40V, VGS=0V | 2 |
| Gate-Body Leakage Current | IGSS | -100 |  | 100 | nA | VGS=±20V, VDS=0V | 2 |
| Gate Threshold Voltage | VGS(th) | 1 | 1.5 | 2 | V | VDS=VGS, ID=250μA | 2 |
| Drain-Source On-State Resistance | RDS(ON) |  | 12 | 16 | mΩ | VGS=10V, ID=8A | 2 |
| Drain-Source On-State Resistance | RDS(ON) |  | 18.9 | 24 | mΩ | VGS=4.5V, ID=4A | 2 |
| Forward Transconductance | gFS | 33 |  |  | S | VDS=5V, ID=8A | 2 |
| Diode Forward Voltage | VSD |  | 0.8 | 1.2 | V | VGS=0V, IS=9A | 2 |

## CAD (KiCad official)

- Symbol: `4884`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `4884-etched.step` / `4884-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `4884.step` / `4884.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HL datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603006596046082048) (5 pp, sha256 `fadbe1dd6a23d696`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/4884-datasheet.pdf)