2EDL05N06PF

Infineon Technologies · Gate Drive ICs · SOP-8

2EDL05N06PF from Infineon Technologies, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Low-side and logic supply voltage, operating range 10 V to 17.5 V for MOSFET types (absolute max 20 V).
2	HIN	input	Logic input for high-side gate driver output (HO), in phase, Schmitt trigger input with hysteresis and pull-down.
3	LIN	input	Logic input for low-side gate driver output (LO), in phase, Schmitt trigger input with hysteresis and pull-down.
4	GND	power_in	Low-side gate drive return and ground reference for logic inputs.
5	LO	output	Low-side driver output with 0.36 A source / 0.7 A sink peak current.
6	VS	power_in	High voltage floating supply return, tolerant to negative transients down to -100 V (tp<300 ns) and max 600 V.
7	HO	output	High-side driver output with 0.36 A source / 0.7 A sink peak current.
8	VB	power_in	High-side gate drive floating supply, max 620 V absolute, VBS operating 10 V to 17.5 V for MOSFET types.

Key specifications

Parameter	Value
Manufacturer	Infineon Technologies
Package	SOP-8
Category	Power Management ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
High side offset voltage VS	VS			600	V	min is VDD-VBS-6	9
High side offset voltage VB	VB			620	V	min is VDD-6	9
High side floating supply voltage (VB vs. VS)	VBS	-1		20	V	internally clamped	9
High side output voltage (VHO vs. VS)	VHO	-0.5			V	max is VB + 0.5	9
Low side supply voltage	VDD	-1		20	V	internally clamped	9
Low side output voltage (VLO vs. VGND)	VLO	-0.5			V	max is VGND + 0.5	9
Input voltage LIN,HIN	VIN	-0.5			V	max is VDD + 0.5	9
Power dissipation DSO8	PD			0.6	W	Ta=25°C	9
Thermal resistance junction to ambient DSO8	Rth(j-a)			195	K/W		9
Junction temperature	TJ			150	°C		9
Storage temperature	TS	-40		150	°C		9
Offset voltage slew rate	dVS/dt			50	V/ns		9
High side offset voltage (required)	VB	7		620	V		10
Low side supply voltage (required)	VDD	10		20	V	internally clamped	10
High side floating supply offset voltage	VS			500	V	min is VDD - VBS -1	10
High side floating supply offset voltage (VB vs. VDD, statically)	VBDD	-1		500	V		10
High side floating supply voltage MOSFET-Types	VBS	10		17.5	V		10
High side output voltage (VHO vs. VS)	VHO	0			V	max is VBS	10
Low side output voltage (VLO vs. VGND)	VLO	0			V	max is VDD	10
Low side supply voltage MOSFET-Types	VDD	10		17.5	V		10
Logic input voltages LIN,HIN	VIN	0		17.5	V		10
Pulse width for ON or OFF MOSFET-Types	tIN	0.3			µs		10
Ambient temperature	Ta	-40		105	°C		10
Thermal coefficient junction to top DSO8	Ψth(j-top)			8	K/W		10
High level input voltage	VIH	1.7	2.1	2.4	V	VDD = VBS = 15V, Ta=25°C	11
Low level input voltage	VIL	0.7	0.9	1.1	V	VDD = VBS = 15V, Ta=25°C	11
High level output voltage LO (VDD-)	VOH		0.45	1	V	IO = -20 mA; printed as VDD -0.45 typ, VDD -1 max	11
Low level output voltage LO (above VGND)	VOL		0.13	0.3	V	IO = 20 mA; printed as VGND+0.13 typ, VGND+0.3 max	11
VDD supply undervoltage positive going threshold MOSFET	VDDUV+	8.3	9.1	9.9	V		11
VBS supply undervoltage positive going threshold MOSFET	VBSUV+	8.3	9.1	9.9	V		11
VDD supply undervoltage negative going threshold MOSFET	VDDUV-	7.5	8.3	9	V		11
VBS supply undervoltage negative going threshold MOSFET	VBSUV-	7.5	8.3	9	V		11
VDD and VBS supply UVLO hysteresis MOSFET	VDDUVH, VBSUVH	0.5	0.9		V		11
High side leakage current betw. VS and GND	ILVS+		1	12.5	µA	VS = 600V	11
Quiescent current VBS supply	IQBS1		170	300	µA	HO = low	11
Quiescent current VDD supply	IQDD1		0.3	0.6	mA	VLIN = float.	11
Quiescent current VDD supply	IQDD2		0.28	0.6	mA	VLIN = 3.3 V, VHIN=0	12
Input bias current	ILIN+	15	35	60	µA	VLIN = 3.3 V	12
Mean output current charging	IO+	0.18	0.23		A	CL = 22 nF	12
Mean output current discharging	IO-	0.39	0.48		A	CL = 22 nF	12
Bootstrap diode forward voltage between VDD and VB	VF,BSD		1	1.2	V	IF = 0.3 mA	12
Bootstrap diode forward current between VDD and VB	IF,BSD	30	55	80	mA	VDD, VB = 4 V	12
Bootstrap diode resistance	RBSD	20	36	54	Ω	VF1 = 4 V, VF2 = 5 V	12
Turn-on propagation delay MOSFET types	ton	210	310	460	ns	VLIN/HIN = 0 or 3.3 V	13
Turn-off propagation delay MOSFET types	toff	200	300	440	ns	VLIN/HIN = 0 or 3.3 V	13
Turn-on rise time	tr		48	80	ns	CL = 1 nF	13
Turn-off fall time	tf		24	40	ns	CL = 1 nF	13
Input filter time HIN MOSFET types	tFILIN	50	100	170	ns	VLIN/HIN = 0 & 3.3 V	13
Input filter time LIN MOSFET types	tFILIN	100	150	250	ns	VLIN/HIN = 0 & 3.3 V	13
Dead time MOSFET types	DT	30	75	140	ns	VLIN/HIN = 0 & 3.3 V	13
Dead time matching MOSFET types	MDT		10	50	ns	ext. dead time 0ns	13
Matching delay ON	MTON		10	60	ns	external dead time > 500 ns	13
Matching delay OFF	MTOFF		10	60	ns	external dead time >500 ns	13
Output pulse width matching MOSFET types	PM		20	70	ns	PWin > 1 µs	13
Peak output current turn on	IOpk+		0.36		A	RL = 0 Ω, tp <10 µs	12
Peak output current turn off	IOpk-		0.7		A	RL = 0 Ω, tp <10 µs	12

CAD (KiCad official)

Symbol: 2EDL05N06PF
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)
3D model files: 2edl05n06pf-etched.step / 2edl05n06pf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 2edl05n06pf.step / 2edl05n06pf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Infineon Technologies datasheet (21 pp, sha256 a53bbbfb0e8aaad4, retrieved 2026-10-23, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# 2EDL05N06PF

**Infineon Technologies** · Gate Drive ICs · SOP-8

2EDL05N06PF from Infineon Technologies, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Low-side and logic supply voltage, operating range 10 V to 17.5 V for MOSFET types (absolute max 20 V). |
| 2 | HIN | input | Logic input for high-side gate driver output (HO), in phase, Schmitt trigger input with hysteresis and pull-down. |
| 3 | LIN | input | Logic input for low-side gate driver output (LO), in phase, Schmitt trigger input with hysteresis and pull-down. |
| 4 | GND | power_in | Low-side gate drive return and ground reference for logic inputs. |
| 5 | LO | output | Low-side driver output with 0.36 A source / 0.7 A sink peak current. |
| 6 | VS | power_in | High voltage floating supply return, tolerant to negative transients down to -100 V (tp<300 ns) and max 600 V. |
| 7 | HO | output | High-side driver output with 0.36 A source / 0.7 A sink peak current. |
| 8 | VB | power_in | High-side gate drive floating supply, max 620 V absolute, VBS operating 10 V to 17.5 V for MOSFET types. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOP-8 |
| Category | Power Management ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High side offset voltage VS | VS |  |  | 600 | V | min is VDD-VBS-6 | 9 |
| High side offset voltage VB | VB |  |  | 620 | V | min is VDD-6 | 9 |
| High side floating supply voltage (VB vs. VS) | VBS | -1 |  | 20 | V | internally clamped | 9 |
| High side output voltage (VHO vs. VS) | VHO | -0.5 |  |  | V | max is VB + 0.5 | 9 |
| Low side supply voltage | VDD | -1 |  | 20 | V | internally clamped | 9 |
| Low side output voltage (VLO vs. VGND) | VLO | -0.5 |  |  | V | max is VGND + 0.5 | 9 |
| Input voltage LIN,HIN | VIN | -0.5 |  |  | V | max is VDD + 0.5 | 9 |
| Power dissipation DSO8 | PD |  |  | 0.6 | W | Ta=25°C | 9 |
| Thermal resistance junction to ambient DSO8 | Rth(j-a) |  |  | 195 | K/W |  | 9 |
| Junction temperature | TJ |  |  | 150 | °C |  | 9 |
| Storage temperature | TS | -40 |  | 150 | °C |  | 9 |
| Offset voltage slew rate | dVS/dt |  |  | 50 | V/ns |  | 9 |
| High side offset voltage (required) | VB | 7 |  | 620 | V |  | 10 |
| Low side supply voltage (required) | VDD | 10 |  | 20 | V | internally clamped | 10 |
| High side floating supply offset voltage | VS |  |  | 500 | V | min is VDD - VBS -1 | 10 |
| High side floating supply offset voltage (VB vs. VDD, statically) | VBDD | -1 |  | 500 | V |  | 10 |
| High side floating supply voltage MOSFET-Types | VBS | 10 |  | 17.5 | V |  | 10 |
| High side output voltage (VHO vs. VS) | VHO | 0 |  |  | V | max is VBS | 10 |
| Low side output voltage (VLO vs. VGND) | VLO | 0 |  |  | V | max is VDD | 10 |
| Low side supply voltage MOSFET-Types | VDD | 10 |  | 17.5 | V |  | 10 |
| Logic input voltages LIN,HIN | VIN | 0 |  | 17.5 | V |  | 10 |
| Pulse width for ON or OFF MOSFET-Types | tIN | 0.3 |  |  | µs |  | 10 |
| Ambient temperature | Ta | -40 |  | 105 | °C |  | 10 |
| Thermal coefficient junction to top DSO8 | Ψth(j-top) |  |  | 8 | K/W |  | 10 |
| High level input voltage | VIH | 1.7 | 2.1 | 2.4 | V | VDD = VBS = 15V, Ta=25°C | 11 |
| Low level input voltage | VIL | 0.7 | 0.9 | 1.1 | V | VDD = VBS = 15V, Ta=25°C | 11 |
| High level output voltage LO (VDD-) | VOH |  | 0.45 | 1 | V | IO = -20 mA; printed as VDD -0.45 typ, VDD -1 max | 11 |
| Low level output voltage LO (above VGND) | VOL |  | 0.13 | 0.3 | V | IO = 20 mA; printed as VGND+0.13 typ, VGND+0.3 max | 11 |
| VDD supply undervoltage positive going threshold MOSFET | VDDUV+ | 8.3 | 9.1 | 9.9 | V |  | 11 |
| VBS supply undervoltage positive going threshold MOSFET | VBSUV+ | 8.3 | 9.1 | 9.9 | V |  | 11 |
| VDD supply undervoltage negative going threshold MOSFET | VDDUV- | 7.5 | 8.3 | 9 | V |  | 11 |
| VBS supply undervoltage negative going threshold MOSFET | VBSUV- | 7.5 | 8.3 | 9 | V |  | 11 |
| VDD and VBS supply UVLO hysteresis MOSFET | VDDUVH, VBSUVH | 0.5 | 0.9 |  | V |  | 11 |
| High side leakage current betw. VS and GND | ILVS+ |  | 1 | 12.5 | µA | VS = 600V | 11 |
| Quiescent current VBS supply | IQBS1 |  | 170 | 300 | µA | HO = low | 11 |
| Quiescent current VDD supply | IQDD1 |  | 0.3 | 0.6 | mA | VLIN = float. | 11 |
| Quiescent current VDD supply | IQDD2 |  | 0.28 | 0.6 | mA | VLIN = 3.3 V, VHIN=0 | 12 |
| Input bias current | ILIN+ | 15 | 35 | 60 | µA | VLIN = 3.3 V | 12 |
| Mean output current charging | IO+ | 0.18 | 0.23 |  | A | CL = 22 nF | 12 |
| Mean output current discharging | IO- | 0.39 | 0.48 |  | A | CL = 22 nF | 12 |
| Bootstrap diode forward voltage between VDD and VB | VF,BSD |  | 1 | 1.2 | V | IF = 0.3 mA | 12 |
| Bootstrap diode forward current between VDD and VB | IF,BSD | 30 | 55 | 80 | mA | VDD, VB = 4 V | 12 |
| Bootstrap diode resistance | RBSD | 20 | 36 | 54 | Ω | VF1 = 4 V, VF2 = 5 V | 12 |
| Turn-on propagation delay MOSFET types | ton | 210 | 310 | 460 | ns | VLIN/HIN = 0 or 3.3 V | 13 |
| Turn-off propagation delay MOSFET types | toff | 200 | 300 | 440 | ns | VLIN/HIN = 0 or 3.3 V | 13 |
| Turn-on rise time | tr |  | 48 | 80 | ns | CL = 1 nF | 13 |
| Turn-off fall time | tf |  | 24 | 40 | ns | CL = 1 nF | 13 |
| Input filter time HIN MOSFET types | tFILIN | 50 | 100 | 170 | ns | VLIN/HIN = 0 & 3.3 V | 13 |
| Input filter time LIN MOSFET types | tFILIN | 100 | 150 | 250 | ns | VLIN/HIN = 0 & 3.3 V | 13 |
| Dead time MOSFET types | DT | 30 | 75 | 140 | ns | VLIN/HIN = 0 & 3.3 V | 13 |
| Dead time matching MOSFET types | MDT |  | 10 | 50 | ns | ext. dead time 0ns | 13 |
| Matching delay ON | MTON |  | 10 | 60 | ns | external dead time > 500 ns | 13 |
| Matching delay OFF | MTOFF |  | 10 | 60 | ns | external dead time >500 ns | 13 |
| Output pulse width matching MOSFET types | PM |  | 20 | 70 | ns | PWin > 1 µs | 13 |
| Peak output current turn on | IOpk+ |  | 0.36 |  | A | RL = 0 Ω, tp <10 µs | 12 |
| Peak output current turn off | IOpk- |  | 0.7 |  | A | RL = 0 Ω, tp <10 µs | 12 |

## CAD (KiCad official)

- Symbol: `2EDL05N06PF`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `2edl05n06pf-etched.step` / `2edl05n06pf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `2edl05n06pf.step` / `2edl05n06pf.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon Technologies datasheet](docs/2edl05n06pf-datasheet.pdf) (21 pp, sha256 `a53bbbfb0e8aaad4`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/2edl05n06pf-datasheet.pdf)