component
25AA160B-I
Public Made by Adomby adom
Microchip Tech Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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25AA160B-I
Microchip Tech · Pre-ordered Chips · SOIC-8
25AA160B-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select input: a low level selects the device, a high level deselects it and forces Standby mode, and SO goes high-impedance when deselected. |
| 2 | SO | tri_state | Serial Data Output: data is shifted out after the falling edge of the serial clock, and the pin is high-impedance when the device is deselected or held. |
| 3 | WP | input | Write-Protect pin: with WPEN set, WP low disables writes to the nonvolatile STATUS register bits, and WP high allows all functions to operate normally. |
| 4 | VSS | power_in | Ground. |
| 5 | SI | input | Serial Data Input: receives instructions, addresses and data, latched on the rising edge of the serial clock. |
| 6 | SCK | input | Serial Clock input that synchronizes communication, with SI latched on the rising edge and SO updated after the falling edge (max clock 10 MHz). |
| 7 | HOLD | input | Hold input: pulled low (while SCK is low) to pause serial communication without resetting the sequence, and must be held high when not in use. |
| 8 | VCC | power_in | Supply voltage, 1.8V to 5.5V for the 25AA160B (absolute maximum 7.0V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | 7 | V | 2 | |||
| Voltage on all inputs and outputs w.r.t. VSS | -0.6 | V | -0.6V to VCC +1.0V | 2 | |||
| Storage temperature | -65 | 150 | °C | 2 | |||
| Ambient temperature under bias | -40 | 125 | °C | 2 | |||
| ESD protection on all pins | 4 | kV | 2 | ||||
| Supply voltage (Industrial) | VCC | 1.8 | 5.5 | V | Industrial (I): TAMB = -40°C to +85°C | 2 | |
| High-level input voltage | VIH1 | 2 | V | VCC ≥ 2.7V (Note); max printed as VCC +1 | 2 | ||
| Low-level input voltage | VIL1 | -0.3 | 0.8 | V | VCC ≥ 2.7V (Note) | 2 | |
| Low-level input voltage | VIL2 | -0.3 | V | VCC < 2.7V (Note); max printed as 0.2 VCC | 2 | ||
| Low-level output voltage | VOL | 0.4 | V | IOL = 2.1 mA | 2 | ||
| Low-level output voltage | VOL | 0.2 | V | IOL = 1.0 mA, VCC < 2.5V | 2 | ||
| Input leakage current | ILI | -1 | 1 | μA | CS = VCC, VIN = VSS TO VCC | 2 | |
| Output leakage current | ILO | -1 | 1 | μA | CS = VCC, VOUT = VSS TO VCC | 2 | |
| Internal capacitance (all inputs and outputs) | CINT | 7 | pF | TAMB = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) | 2 | ||
| Read operating current | ICC Read | 6 | mA | VCC = 5.5V; FCLK = 10.0 MHz; SO = Open | 2 | ||
| Read operating current | ICC Read | 2.5 | mA | VCC = 2.5V; FCLK = 5.0 MHz; SO = Open | 2 | ||
| Write operating current | ICC Write | 3 | mA | VCC = 5.5V | 2 | ||
| Standby current | ICCS | 5 | μA | CS = VCC = 5.5V, Inputs tied to VCC or VSS, TAMB = -40°C TO +125°C | 2 | ||
| Standby current | ICCS | 1 | μA | CS = VCC = 2.5V, Inputs tied to VCC or VSS, TAMB = -40°C TO +85°C | 2 | ||
| Clock frequency | FCLK | 10 | MHz | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Clock frequency | FCLK | 5 | MHz | 2.5V ≤ VCC < 4.5V | 3 | ||
| Clock frequency | FCLK | 3 | MHz | 1.8V ≤ VCC < 2.5V | 3 | ||
| CS setup time | TCSS | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| CS setup time | TCSS | 100 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| CS setup time | TCSS | 150 | ns | 1.8V ≤ VCC < 2.5V | 3 | ||
| CS hold time | TCSH | 100 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| CS hold time | TCSH | 200 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| CS hold time | TCSH | 250 | ns | 1.8V ≤ VCC < 2.5V | 3 | ||
| Data setup time | Tsu | 10 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Data setup time | Tsu | 20 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| Data setup time | Tsu | 30 | ns | 1.8V ≤ VCC < 2.5V | 3 | ||
| Data hold time | THD | 20 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Data hold time | THD | 40 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| Data hold time | THD | 50 | ns | 1.8V ≤ VCC < 2.5V | 3 | ||
| Clock high time | THI | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Clock high time | THI | 100 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| Clock high time | THI | 150 | ns | 1.8V ≤ VCC < 2.5V | 3 | ||
| Clock low time | TLO | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Clock low time | TLO | 100 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| Clock low time | TLO | 150 | ns | 1.8V ≤ VCC < 2.5V | 3 | ||
| Output valid from clock low | TV | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Output valid from clock low | TV | 100 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| Output valid from clock low | TV | 160 | ns | 1.8V ≤ VCC < 2.5V | 3 | ||
| Output disable time | TDIS | 40 | ns | 4.5V ≤ VCC ≤ 5.5V (Note 1) | 3 | ||
| Output disable time | TDIS | 80 | ns | 2.5V ≤ VCC ≤ 4.5V (Note 1) | 3 | ||
| Output disable time | TDIS | 160 | ns | 1.8V ≤ VCC ≤ 2.5V (Note 1) | 3 | ||
| HOLD setup time | THS | 20 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| HOLD setup time | THS | 40 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| HOLD setup time | THS | 80 | ns | 1.8V ≤ VCC < 2.5V | 3 | ||
| HOLD hold time | THH | 20 | ns | 4.5V ≤ VCC ≤ 5.5V | 4 | ||
| HOLD hold time | THH | 40 | ns | 2.5V ≤ VCC < 4.5V | 4 | ||
| HOLD hold time | THH | 80 | ns | 1.8V ≤ VCC < 2.5V | 4 | ||
| HOLD low to output high-Z | THZ | 30 | ns | 4.5V ≤ VCC ≤ 5.5V (Note 1) | 4 | ||
| HOLD low to output high-Z | THZ | 60 | ns | 2.5V ≤ VCC < 4.5V (Note 1) | 4 | ||
| HOLD low to output high-Z | THZ | 160 | ns | 1.8V ≤ VCC < 2.5V (Note 1) | 4 | ||
| HOLD high to output valid | THV | 30 | ns | 4.5V ≤ VCC ≤ 5.5V | 4 | ||
| HOLD high to output valid | THV | 60 | ns | 2.5V ≤ VCC < 4.5V | 4 | ||
| HOLD high to output valid | THV | 160 | ns | 1.8V ≤ VCC < 2.5V | 4 | ||
| Internal write cycle time | TWC | 5 | ms | (NOTE 3) | 4 |
CAD (KiCad official)
- Symbol:
25AA160B-I - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
25aa160b-i-etched.step/25aa160b-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);25aa160b-i.step/25aa160b-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (26 pp, sha256
c603a0d9ffe61e4b, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 25AA160B-I
**Microchip Tech** · Pre-ordered Chips · SOIC-8
25AA160B-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select input: a low level selects the device, a high level deselects it and forces Standby mode, and SO goes high-impedance when deselected. |
| 2 | SO | tri_state | Serial Data Output: data is shifted out after the falling edge of the serial clock, and the pin is high-impedance when the device is deselected or held. |
| 3 | WP | input | Write-Protect pin: with WPEN set, WP low disables writes to the nonvolatile STATUS register bits, and WP high allows all functions to operate normally. |
| 4 | VSS | power_in | Ground. |
| 5 | SI | input | Serial Data Input: receives instructions, addresses and data, latched on the rising edge of the serial clock. |
| 6 | SCK | input | Serial Clock input that synchronizes communication, with SI latched on the rising edge and SO updated after the falling edge (max clock 10 MHz). |
| 7 | HOLD | input | Hold input: pulled low (while SCK is low) to pause serial communication without resetting the sequence, and must be held high when not in use. |
| 8 | VCC | power_in | Supply voltage, 1.8V to 5.5V for the 25AA160B (absolute maximum 7.0V). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | | | 7 | V | | 2 |
| Voltage on all inputs and outputs w.r.t. VSS | | -0.6 | | | V | -0.6V to VCC +1.0V | 2 |
| Storage temperature | | -65 | | 150 | °C | | 2 |
| Ambient temperature under bias | | -40 | | 125 | °C | | 2 |
| ESD protection on all pins | | | | 4 | kV | | 2 |
| Supply voltage (Industrial) | VCC | 1.8 | | 5.5 | V | Industrial (I): TAMB = -40°C to +85°C | 2 |
| High-level input voltage | VIH1 | 2 | | | V | VCC ≥ 2.7V (Note); max printed as VCC +1 | 2 |
| Low-level input voltage | VIL1 | -0.3 | | 0.8 | V | VCC ≥ 2.7V (Note) | 2 |
| Low-level input voltage | VIL2 | -0.3 | | | V | VCC < 2.7V (Note); max printed as 0.2 VCC | 2 |
| Low-level output voltage | VOL | | | 0.4 | V | IOL = 2.1 mA | 2 |
| Low-level output voltage | VOL | | | 0.2 | V | IOL = 1.0 mA, VCC < 2.5V | 2 |
| Input leakage current | ILI | -1 | | 1 | μA | CS = VCC, VIN = VSS TO VCC | 2 |
| Output leakage current | ILO | -1 | | 1 | μA | CS = VCC, VOUT = VSS TO VCC | 2 |
| Internal capacitance (all inputs and outputs) | CINT | | | 7 | pF | TAMB = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) | 2 |
| Read operating current | ICC Read | | | 6 | mA | VCC = 5.5V; FCLK = 10.0 MHz; SO = Open | 2 |
| Read operating current | ICC Read | | | 2.5 | mA | VCC = 2.5V; FCLK = 5.0 MHz; SO = Open | 2 |
| Write operating current | ICC Write | | | 3 | mA | VCC = 5.5V | 2 |
| Standby current | ICCS | | | 5 | μA | CS = VCC = 5.5V, Inputs tied to VCC or VSS, TAMB = -40°C TO +125°C | 2 |
| Standby current | ICCS | | | 1 | μA | CS = VCC = 2.5V, Inputs tied to VCC or VSS, TAMB = -40°C TO +85°C | 2 |
| Clock frequency | FCLK | | | 10 | MHz | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Clock frequency | FCLK | | | 5 | MHz | 2.5V ≤ VCC < 4.5V | 3 |
| Clock frequency | FCLK | | | 3 | MHz | 1.8V ≤ VCC < 2.5V | 3 |
| CS setup time | TCSS | 50 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| CS setup time | TCSS | 100 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| CS setup time | TCSS | 150 | | | ns | 1.8V ≤ VCC < 2.5V | 3 |
| CS hold time | TCSH | 100 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| CS hold time | TCSH | 200 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| CS hold time | TCSH | 250 | | | ns | 1.8V ≤ VCC < 2.5V | 3 |
| Data setup time | Tsu | 10 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Data setup time | Tsu | 20 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| Data setup time | Tsu | 30 | | | ns | 1.8V ≤ VCC < 2.5V | 3 |
| Data hold time | THD | 20 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Data hold time | THD | 40 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| Data hold time | THD | 50 | | | ns | 1.8V ≤ VCC < 2.5V | 3 |
| Clock high time | THI | 50 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Clock high time | THI | 100 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| Clock high time | THI | 150 | | | ns | 1.8V ≤ VCC < 2.5V | 3 |
| Clock low time | TLO | 50 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Clock low time | TLO | 100 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| Clock low time | TLO | 150 | | | ns | 1.8V ≤ VCC < 2.5V | 3 |
| Output valid from clock low | TV | | | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Output valid from clock low | TV | | | 100 | ns | 2.5V ≤ VCC < 4.5V | 3 |
| Output valid from clock low | TV | | | 160 | ns | 1.8V ≤ VCC < 2.5V | 3 |
| Output disable time | TDIS | | | 40 | ns | 4.5V ≤ VCC ≤ 5.5V (Note 1) | 3 |
| Output disable time | TDIS | | | 80 | ns | 2.5V ≤ VCC ≤ 4.5V (Note 1) | 3 |
| Output disable time | TDIS | | | 160 | ns | 1.8V ≤ VCC ≤ 2.5V (Note 1) | 3 |
| HOLD setup time | THS | 20 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| HOLD setup time | THS | 40 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| HOLD setup time | THS | 80 | | | ns | 1.8V ≤ VCC < 2.5V | 3 |
| HOLD hold time | THH | 20 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 4 |
| HOLD hold time | THH | 40 | | | ns | 2.5V ≤ VCC < 4.5V | 4 |
| HOLD hold time | THH | 80 | | | ns | 1.8V ≤ VCC < 2.5V | 4 |
| HOLD low to output high-Z | THZ | 30 | | | ns | 4.5V ≤ VCC ≤ 5.5V (Note 1) | 4 |
| HOLD low to output high-Z | THZ | 60 | | | ns | 2.5V ≤ VCC < 4.5V (Note 1) | 4 |
| HOLD low to output high-Z | THZ | 160 | | | ns | 1.8V ≤ VCC < 2.5V (Note 1) | 4 |
| HOLD high to output valid | THV | 30 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 4 |
| HOLD high to output valid | THV | 60 | | | ns | 2.5V ≤ VCC < 4.5V | 4 |
| HOLD high to output valid | THV | 160 | | | ns | 1.8V ≤ VCC < 2.5V | 4 |
| Internal write cycle time | TWC | | | 5 | ms | (NOTE 3) | 4 |
## CAD (KiCad official)
- Symbol: `25AA160B-I`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `25aa160b-i-etched.step` / `25aa160b-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `25aa160b-i.step` / `25aa160b-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/25aa160b-i-datasheet.pdf) (26 pp, sha256 `c603a0d9ffe61e4b`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/25aa160b-i-datasheet.pdf)