component
24C64BN
Public Made by Adomby adom
XBLW EEPROM, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
Publish 0.2.1
ba95cfd
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{
"schema_version": 1,
"type": "component",
"slug": "24c64bn",
"title": "24C64BN",
"brief": "XBLW EEPROM, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
"version": "0.2.1",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"memory",
"24c64bn"
],
"component": {
"mpn": "24C64BN",
"manufacturer": "XBLW",
"package": "SOP-8",
"pin_count": 8,
"category": "Memory",
"subcategory": "EEPROM",
"datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2310191805_XBLW-24C64BN-XBLW_C18723547.pdf",
"parts": {
"symbol": "24c64bn.kicad_sym",
"footprint": "24c64bn.kicad_mod",
"model_3d": "24c64bn-hero.glb",
"model_3d_plain": "24c64bn.glb",
"model_3d_step": "24c64bn-etched.step",
"model_3d_step_plain": "24c64bn.step",
"lbr": "24c64bn.lbr"
},
"distributor_links": {},
"pins": [
{
"number": "1",
"name": "A0",
"type": "input",
"description": "Device address input bit 0. Hard-wire to VIH or VIL to set the least-significant chip-select address bit; matched against the 5th address bit sent on the I2C bus. Internally pulled to VIL if left unconnected."
},
{
"number": "2",
"name": "A1",
"type": "input",
"description": "Device address input bit 1. Hard-wire to VIH or VIL to set the middle chip-select address bit; matched against the 6th address bit sent on the I2C bus. Internally recognized as VIL if left floating."
},
{
"number": "3",
"name": "A2",
"type": "input",
"description": "Device address input bit 2. Hard-wire to VIH or VIL to set the most-significant chip-select address bit; matched against the 7th address bit sent on the I2C bus. Internally recognized as VIL if left floating."
},
{
"number": "4",
"name": "GND",
"type": "power_in",
"description": "Device ground reference (0 V). Common return for VCC and all logic signals."
},
{
"number": "5",
"name": "SDA",
"type": "bidirectional",
"description": "I2C serial data line. Bi-directional, open-drain output - requires an external pull-up resistor to VCC and can be wire-OR'ed with other open-drain devices on the bus."
},
{
"number": "6",
"name": "SCL",
"type": "input",
"description": "I2C serial clock input. Data on SDA is latched into the EEPROM on the rising edge; data is clocked out on the falling edge. Rated 400 kHz at 1.8 V and up to 1 MHz at 2.5-5.5 V."
},
{
"number": "7",
"name": "WP",
"type": "input",
"description": "Hardware write-protect input. Tie to VIL (or leave unconnected) to allow programming of the EEPROM array; tie to VIH / VCC to disable all program/erase operations. Read operations are unaffected by WP state."
},
{
"number": "8",
"name": "VCC",
"type": "power_in",
"description": "Positive supply input. Operating range 1.8 V to 5.5 V; absolute maximum 8 V. Bypass to GND with a local 100 nF ceramic capacitor."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2310191805_XBLW-24C64BN-XBLW_C18723547.pdf",
"pages": 18,
"sha256": "c0329401d1e9b2e0",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"pin1": {
"pad": "1",
"at": [
-2.475,
-1.905
],
"corner": "top-left",
"source": "silk-marker",
"derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",
"mark": "drawn"
},
"models_3d": [
{
"file": "24c64bn.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
4.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "24c64bn-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
4.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "3b10d228c55c2ef07964a4d00beef44ff2df93092d07022737efa2167a6a16ac",
"checked": "2026-10-23",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "XBLW",
"Package": "SOP-8",
"Category": "Memory",
"Pins": "8"
}
},
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"24c64bn"
],
"discovery_pitch": "24C64BN (XBLW) component page with datasheet-verified CAD.",
"author": {
"name": "Ray"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"24c64bn.kicad_sym",
"24c64bn.kicad_mod",
"24c64bn.glb",
"24c64bn.step",
"24c64bn-etched.step",
"24c64bn.lbr",
"docs/hero.png",
"docs/24c64bn-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"pads.json",
"24c64bn-hero.glb",
"24c64bn-hero.overlay.json"
],
"visibility": "public",
"updated_at": "2026-09-24T14:32:20.237Z",
"description": "XBLW EEPROM, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",
"org": "adom"
}