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ZJG4438ASEBR

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by Ray

ZJW Analog Switches, Multiplexers, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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ZJG4438ASEBR

ZJW · Analog Switches, Multiplexers · SOIC-16

ZJG4438ASEBR from ZJW, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Logic control input LSB of the 3-bit binary channel-select address. TTL/CMOS-compatible: VINL ≤ 0.8 V, VINH ≥ 2.4 V, input current ≤ 1 µA.
2 EN input Active-high digital enable. When low the device is disabled and all switches are off; when high the Ax logic inputs determine which of S1..S8 is connected to D. TTL/CMOS-compatible thresholds (VINL ≤ 0.8 V, VINH ≥ 2.4 V).
3 VSS power_in Most-negative power-supply potential (typically -15 V; range -5 V to -18 V for dual-supply operation). Tie to GND in single-supply applications.
4 S1 bidirectional Source terminal 1 of the 8:1 analog multiplexer. Can be an input or output; connected to D when A2/A1/A0 = 000 and EN = 1. Ron ≈ 270 Ω typ, ±50 V overvoltage protected.
5 S2 bidirectional Source terminal 2 of the 8:1 analog multiplexer. Selected to D when A2/A1/A0 = 001 and EN = 1. Ron ≈ 270 Ω typ, ±50 V fault protected.
6 S3 bidirectional Source terminal 3 of the 8:1 analog multiplexer. Selected to D when A2/A1/A0 = 010 and EN = 1.
7 S4 bidirectional Source terminal 4 of the 8:1 analog multiplexer. Selected to D when A2/A1/A0 = 011 and EN = 1.
8 D bidirectional Common drain terminal - the single pole of the 8:1 multiplexer. Connects to the selected Sx pin when EN = 1. Can be driven as input or read as output.
9 S8 bidirectional Source terminal 8 of the 8:1 analog multiplexer. Selected to D when A2/A1/A0 = 111 and EN = 1.
10 S7 bidirectional Source terminal 7 of the 8:1 analog multiplexer. Selected to D when A2/A1/A0 = 110 and EN = 1.
11 S6 bidirectional Source terminal 6 of the 8:1 analog multiplexer. Selected to D when A2/A1/A0 = 101 and EN = 1.
12 S5 bidirectional Source terminal 5 of the 8:1 analog multiplexer. Selected to D when A2/A1/A0 = 100 and EN = 1.
13 VDD power_in Most-positive power-supply potential (typically +15 V; range +5 V to +18 V for dual-supply operation). Total supply (VDD − VSS) ≤ 40 V absolute maximum.
14 GND power_in Ground (0 V) reference for the digital logic and address decoder.
15 A2 input Logic control input MSB of the 3-bit binary channel-select address. TTL/CMOS-compatible thresholds (VINL ≤ 0.8 V, VINH ≥ 2.4 V).
16 A1 input Logic control input (middle bit) of the 3-bit binary channel-select address. TTL/CMOS-compatible thresholds (VINL ≤ 0.8 V, VINH ≥ 2.4 V).

Key specifications

Parameter Value
Manufacturer ZJW
Package SOIC-16
Category Interface
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • ZJG4438ASEBT
  • ZJG4438ASEBR
  • ZJG4438AUEBT
  • ZJG4438AUEBR

CAD (KiCad official)

  • Symbol: ZJG4438ASEBR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ZJW datasheet (None pp, sha256 549c904e45ebd9ca, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF