component
XRP6272IDBTR-F
Public Unreviewedby Ray
MaxLinear Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXRP6272IDBTR-F
MaxLinear · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8-EP
XRP6272IDBTR-F from MaxLinear, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable pin. Drive above 1.6V (min) to enable the regulator; drive below 0.4V (max) to shut down the device (shutdown current 0.01µA typ). Absolute max 7.0V. |
| 2 | VIN | power_in | Power input pin, 1.8V to 6V operating range (absolute max 7.0V). Must be closely decoupled to GND with a 4.7µF or greater ceramic capacitor. |
| 3 | VOUT | power_out | Regulator output pin, up to 2A continuous. Requires a 4.7µF ceramic output capacitor (10µF recommended for VOUT ≤ 1.8V). |
| 4 | ADJ | input | Adjustable pin. Connect to GND for the internal fixed 5V output setting; otherwise tie to an external R1/R2 feedback divider to set VOUT = VREF × (1 + R1/R2), where VREF = 0.7V nominal. ADJ threshold 0.1V typ, ADJ pin current 10nA typ. |
| 5 | GND | power_in | Ground signal pin. Tie to system ground along with pin 8 and the exposed pad. |
| 6 | BP | passive | Bypass pin for the internal 0.7V reference buffer. Connect a 22nF capacitor to GND to reduce output noise (24µVrms typ with CBP = 22nF). May be left floating if noise filtering is not required. Absolute max 7.0V. |
| 7 | PGOOD | output | Power Good open-drain output. Asserts (releases high via external pull-up) when VOUT rises above ~90-93% of nominal after a 0.5-5ms delay; sinks up to IPGOOD = 10mA (0.2-0.4V VOL). |
| 8 | GND | power_in | Ground signal pin. Tie to system ground along with pin 5 and the exposed pad. |
| EP | GND | power_in | Exposed thermal pad on the SOIC-8 (HSOIC) package. Must be connected to GND and to a copper thermal plane to achieve θJA = 60°C/W. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MaxLinear |
| Package | SOIC-8-EP |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
XRP6272IDBTR-FXRP6272IDBTR-FITC5TR-F
CAD (KiCad official)
- Symbol:
XRP6272IDBTR-F - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MaxLinear datasheet (13 pp, sha256
aae5697cf16250bf, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).