component
xl9910
Public Unreviewedby Ray
XINLUDA LED Drivers, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
README
markdownXL9910
XINLUDA · LED Drivers · SOP-8
XL9910 from XINLUDA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input of the internal 8.0-450V linear regulator. Provides bias to the IC; input current ≈ 1.0mA + Qg·fS. May be limited by package power dissipation at high VIN; a series Zener can offload dissipation for high-voltage operation. |
| 2 | CS | input | Current-sense input. Senses external N-FET current via an external sense resistor RCS. When CS exceeds the lower of the internal 250mV reference or the LD-pin voltage, the GATE output is turned off. Includes an internal 150-280ns leading-edge blanking. |
| 3 | GND | power_in | Ground return for all internal circuitry. Must be electrically connected to the power-train ground with a low-impedance path to minimize switching noise on CS. |
| 4 | GATE | output | Gate driver output for the external N-channel power MOSFET. Sourcing/sinking capability ≈ 165mA; typical rise/fall times ≈ 30ns with 500pF load. Recommended external FET Qg ≤ 25nC at fS ≤ 100kHz (≤ 15nC above 100kHz). |
| 5 | PWMD | input | PWM dimming input. Pulling low (VIL ≤ 0.8V) disables the GATE driver; pulling high (VIH ≥ 2.0V) enables normal operation. Internal ~100kΩ pull-down. Response is near-instantaneous; tie to VDD to disable PWM dimming permanently. |
| 6 | VDD | power_out | Internally regulated 7.5V supply rail (7.25-7.75V) for all internal circuits. Must be bypassed to GND with a low-ESR capacitor ≥ 0.1μF. May be driven externally to bypass the internal regulator, but must not exceed 12V. |
| 7 | LD | input | Linear dimming input. Sets the current-sense threshold when the applied voltage is below the internal 250mV reference. Accepts a 0-250mV analog voltage or a divider from VDD; tie to VDD to use the internal 250mV threshold. Cannot force LED current to zero (use PWMD for that). |
| 8 | RT | passive | Oscillator timing pin. Per-cycle time set by tOSC(μs) = (RT(kΩ)+22)/25. Resistor from RT to GND → constant-frequency mode; resistor from RT to GATE → constant off-time mode. Typical fOSC ≈ 100kHz at RT = 226kΩ, ≈ 25kHz at RT = 1.00MΩ. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOP-8 |
| Category | LED-drv |
| Pins | 8 |
Ordering variants
XL9910
CAD (KiCad official)
- Symbol:
XL9910 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (None pp, sha256
11af739564ea0ac5, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).