XL74HC597 from XINLUDA, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	D1	input	Parallel data input bit 1 to the 8-bit input storage (flip-flop) register. CMOS-level input; latched to the storage register on the rising edge of STCP.
2	D2	input	Parallel data input bit 2 to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP.
3	D3	input	Parallel data input bit 3 to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP.
4	D4	input	Parallel data input bit 4 to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP.
5	D5	input	Parallel data input bit 5 to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP.
6	D6	input	Parallel data input bit 6 to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP.
7	D7	input	Parallel data input bit 7 (MSB) to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP.
8	GND	power_in	Ground reference (0 V). All voltages are referenced to this pin.
9	Q	output	Serial data output - tap from the last stage of the 8-bit shift register. Push-pull CMOS output rated for IO up to ±25 mA (absolute max); VOH ≥ VCC-0.1 V at IO = -20 µA.
10	MR	input	Asynchronous master reset input, active LOW. Driving MR LOW while PL is HIGH clears the 8-bit shift register regardless of the clocks.
11	SHCP	input	Shift-register clock input. Positive edge-triggered (LOW-to-HIGH): each rising edge shifts DS into Q0 and propagates all bits toward Q. Max frequency 30 MHz min at VCC = 4.5 V (typ 87 MHz).
12	STCP	input	Storage-register clock input. Positive edge-triggered (LOW-to-HIGH): each rising edge loads the D0-D7 parallel inputs into the 8-bit input storage (flip-flop) register.
13	PL	input	Parallel-load input, active LOW. Asserting PL LOW (with MR HIGH) transfers the contents of the input storage register in parallel into the 8-bit shift register.
14	DS	input	Serial data input to the shift register. Sampled on the rising edge of SHCP and loaded into Q0 during serial-shift operation.
15	D0	input	Parallel data input bit 0 (LSB) to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP.
16	VCC	power_in	Supply voltage. Recommended operating range 2.0 V to 6.0 V (typ 5.0 V); absolute maximum -0.5 V to +7 V.

Key specifications

Parameter	Value
Manufacturer	XINLUDA
Package	SOP-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

XL74HC597
XL74HC597-TS
XL74HC597XD74HC597

CAD (KiCad official)

Symbol: XL74HC597
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`xl74hc597.step`	217 KB	You want the bare part, or you mark your own boards.
`xl74hc597-etched.step`	2.0 MB	You want the part with `XL74HC597` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 510 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XINLUDA datasheet (16 pp, sha256 8e0ebbf85b427db7, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF