XL74HC595 from XINLUDA, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	QB	tri_state	Parallel tri-state output bit B from the 8-bit storage register. Drives up to -6 mA / +6 mA at VCC=4.5V and -7.8 mA / +7.8 mA at VCC=6V.
2	QC	tri_state	Parallel tri-state output bit C from the 8-bit storage register. Enabled when G is low.
3	QD	tri_state	Parallel tri-state output bit D from the 8-bit storage register. Enabled when G is low.
4	QE	tri_state	Parallel tri-state output bit E from the 8-bit storage register. Enabled when G is low.
5	QF	tri_state	Parallel tri-state output bit F from the 8-bit storage register. Enabled when G is low.
6	QG	tri_state	Parallel tri-state output bit G from the 8-bit storage register. Enabled when G is low.
7	QH	tri_state	Parallel tri-state output bit H (MSB) from the 8-bit storage register. Enabled when G is low.
8	GND	power_in	Digital ground reference (0 V).
9	Q'H	output	Serial data output from the shift register (not tri-stated). Used for cascading multiple XL74HC595 devices; connect to SER of the next stage.
10	SCLR	input	Shift register clear, active low. When low, the shift register contents are cleared (Q'H = 0). Does not affect the storage register.
11	SCK	input	Shift register clock input. Rising edge shifts data from SER into the shift register. Max 30 MHz typical (VCC=6V, up to 108 MHz typ per AC characteristics).
12	RCK	input	Storage register (latch) clock input. Rising edge latches the current shift register contents into the 8-bit storage register, updating QA-QH.
13	G	input	Output Enable, active low. When low, QA-QH are driven from the storage register; when high, QA-QH are in high-impedance state. Does not affect Q'H.
14	SER	input	Serial data input. Value present at SER is shifted into the shift register on the rising edge of SCK.
15	QA	tri_state	Parallel tri-state output bit A (LSB) from the 8-bit storage register. Enabled when G is low.
16	VCC	power_in	Digital power supply, 2 V to 6 V (absolute max +7 V). Bypass with a 100 nF ceramic capacitor close to the pin.

Key specifications

Parameter	Value
Manufacturer	XINLUDA
Package	SOP-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

XL74HC595
XL74HC595TS

CAD (KiCad official)

Symbol: XL74HC595
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XINLUDA datasheet (13 pp, sha256 e0ba2b7daef7908f, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF