Loads on click. Unloads when scrolled away or the tab is hidden.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

PCB Footprint

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Loads on click. Unloads when scrolled away or the tab is hidden.
Download PDF
Contents

README

markdown

XL1040

XINLUDA · CAN Controllers · SOIC-8

XL1040 from XINLUDA, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXD input Transmit data input from the CAN controller. Logic-low drives the bus dominant; logic-high (or float) leaves the bus recessive. Input thresholds VIL ≤ 0.8 V, VIH ≥ 2 V (relative to VCC). A dominant time-out (~4 ms typ) prevents a stuck-low TXD from permanently holding the bus dominant.
2 GND power_in Ground / power supply return.
3 VCC power_in Supply voltage input, VCC = 5 V ± 10% (absolute max -0.3 V to +6 V). Decouple close to the pin.
4 RXD output Receive data output to the CAN controller; reflects the state of the differential bus. Drives high (VOH ≥ 4 V at IO = -2 mA) for recessive and low (VOL ≤ 0.4 V at IO = 2 mA) for dominant.
5 SPLIT output Common-mode stabilization output, nominally VCC/2 (~2.5 V, range 2-3 V). Typically connected to the midpoint of a split-termination network to stabilize the bus common-mode voltage and improve EMC.
6 CANL bidirectional Low-level CAN bus line (differential). Dominant output ≈ 1.5 V; recessive ≈ 2.5 V. Withstands bus-side voltages of -27 V to +40 V and transient events per automotive requirements.
7 CANH bidirectional High-level CAN bus line (differential). Dominant output ≈ 3.5 V; recessive ≈ 2.5 V. Withstands bus-side voltages of -27 V to +40 V and transient events per automotive requirements.
8 STB input Mode select input. Low = high-speed (normal) mode; high (or float) = standby mode with remote wake-up via the bus. In standby the device draws only ~10 µA typical.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package SOIC-8
Category Interface
Pins 8

CAD (KiCad official)

  • Symbol: XL1040
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
xl1040.step 122 KB You want the bare part, or you mark your own boards.
xl1040-etched.step 1.3 MB You want the part with XL1040 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 340 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (14 pp, sha256 c365483d2adc9f30, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF