component
XD74LS283
Public Unreviewedby Ray
XINLUDA Specialty Logic, DIP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXD74LS283
XINLUDA · Specialty Logic · DIP-16
XD74LS283 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Σ2 | output | Sum output bit 2 (Σ2). Active-high LSTTL output; VOH ≥ 2.7 V at IOH = -400 μA, VOL ≤ 0.5 V at IOL = 8 mA. |
| 2 | B2 | input | B operand input bit 2. LSTTL input; VIH ≥ 2 V, VIL ≤ 0.8 V. Low-level input current -0.8 mA max. |
| 3 | A2 | input | A operand input bit 2. LSTTL input; VIH ≥ 2 V, VIL ≤ 0.8 V. |
| 4 | Σ1 | output | Sum output bit 1 (Σ1, LSB). Active-high LSTTL output. |
| 5 | A1 | input | A operand input bit 1 (LSB). LSTTL input; VIH ≥ 2 V, VIL ≤ 0.8 V. |
| 6 | B1 | input | B operand input bit 1 (LSB). LSTTL input; VIH ≥ 2 V, VIL ≤ 0.8 V. |
| 7 | C0 | input | Carry input to the low-order (bit 1) stage. LSTTL input with slightly lower input current than A/B inputs (IIL = -0.4 mA, IIH = 20 μA). |
| 8 | GND | power_in | Ground reference (0 V). Located on corner pin to simplify PCB layout. |
| 9 | C4 | output | Carry output from the high-order (bit 4) stage. Active-high LSTTL output; propagation delay from C0 typically 11 ns. |
| 10 | Σ4 | output | Sum output bit 4 (MSB). Active-high LSTTL output. |
| 11 | B4 | input | B operand input bit 4 (MSB). LSTTL input; VIH ≥ 2 V, VIL ≤ 0.8 V. |
| 12 | A4 | input | A operand input bit 4 (MSB). LSTTL input; VIH ≥ 2 V, VIL ≤ 0.8 V. |
| 13 | Σ3 | output | Sum output bit 3 (Σ3). Active-high LSTTL output. |
| 14 | A3 | input | A operand input bit 3. LSTTL input; VIH ≥ 2 V, VIL ≤ 0.8 V. |
| 15 | B3 | input | B operand input bit 3. LSTTL input; VIH ≥ 2 V, VIL ≤ 0.8 V. |
| 16 | VCC | power_in | Positive supply. Recommended 4.75 V / 5 V / 5.25 V; absolute max 7 V. ICC typically 22 mA, 39 mA max. Located on corner pin to simplify PCB layout. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
Ordering variants
Same part, different packaging or reel option.
XD74LS283
CAD (KiCad official)
- Symbol:
XD74LS283 - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (7 pp, sha256
540a2688793c0ad4, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).