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Contents

Pinout
Key specifications
Ordering variants
CAD (KiCad official)
Provenance

README

markdown

XC9572XL-10VQG64C

AMD XILINX · Programmable Logic Device (CPLDs/FPGAs) · LQFP-64(10x10)

XC9572XL-10VQG64C from AMD XILINX, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IO_FB2_MC10	bidirectional	User I/O tied to Function Block 2, Macrocell 10. 5 V / 3.3 V / 2.5 V tolerant, referenced to VCCIO.
2	IO_GTS2_FB2_MC11	bidirectional	User I/O with global tri-state control GTS2 alternate function (FB2, MC11). Global control pin.
3	VCCINT	power_in	3.3 V core supply (VCCINT). Range 3.0-3.6 V.
4	IO_FB2_MC12	bidirectional	User I/O (FB2, MC12).
5	IO_GTS1_FB2_MC14	bidirectional	User I/O with global tri-state control GTS1 alternate function (FB2, MC14) on VQ64.
6	IO_FB2_MC15	bidirectional	User I/O (FB2, MC15).
7	IO_FB2_MC17	bidirectional	User I/O (FB2, MC17).
8	IO_FB1_MC2	bidirectional	User I/O (FB1, MC2).
9	IO_FB1_MC5	bidirectional	User I/O (FB1, MC5).
10	IO_FB1_MC6	bidirectional	User I/O (FB1, MC6).
11	IO_FB1_MC8	bidirectional	User I/O (FB1, MC8).
12	IO_FB1_MC3	bidirectional	User I/O (FB1, MC3).
13	IO_FB1_MC4	bidirectional	User I/O (FB1, MC4).
14	GND	power_in	Ground reference (0 V).
15	IO_GCK1_FB1_MC9	bidirectional	User I/O with global clock GCK1 alternate function (FB1, MC9). Drives the global clock network. Global control pin.
16	IO_GCK2_FB1_MC11	bidirectional	User I/O with global clock GCK2 alternate function (FB1, MC11). Global control pin.
17	IO_GCK3_FB1_MC14	bidirectional	User I/O with global clock GCK3 alternate function (FB1, MC14). Global control pin.
18	IO_FB1_MC10	bidirectional	User I/O (FB1, MC10).
19	IO_FB1_MC15	bidirectional	User I/O (FB1, MC15).
20	IO_FB1_MC17	bidirectional	User I/O (FB1, MC17).
21	GND	power_in	Ground reference (0 V).
22	IO_FB3_MC2	bidirectional	User I/O (FB3, MC2).
23	IO_FB1_MC12	bidirectional	User I/O (FB1, MC12).
24	IO_FB3_MC5	bidirectional	User I/O (FB3, MC5).
25	IO_FB3_MC8	bidirectional	User I/O (FB3, MC8).
26	VCCIO	power_in	I/O bank supply (VCCIO). 3.0-3.6 V for 3.3 V I/O or 2.3-2.7 V for 2.5 V I/O; sets the output-driver rail.
27	IO_FB3_MC9	bidirectional	User I/O (FB3, MC9).
28	TDI	input	IEEE 1149.1 JTAG Test Data In. Serial data input to the boundary-scan / ISP shift register.
29	TMS	input	IEEE 1149.1 JTAG Test Mode Select. Drives the TAP controller state machine.
30	TCK	input	IEEE 1149.1 JTAG Test Clock input. Clocks the boundary-scan / in-system programming interface.
31	IO_FB3_MC3	bidirectional	User I/O (FB3, MC3).
32	IO_FB3_MC4	bidirectional	User I/O (FB3, MC4).
33	IO_FB3_MC11	bidirectional	User I/O (FB3, MC11).
34	IO_FB3_MC6	bidirectional	User I/O (FB3, MC6).
35	IO_FB3_MC14	bidirectional	User I/O (FB3, MC14).
36	IO_FB3_MC15	bidirectional	User I/O (FB3, MC15).
37	VCCINT	power_in	3.3 V core supply (VCCINT). Range 3.0-3.6 V.
38	IO_FB3_MC17	bidirectional	User I/O (FB3, MC17).
39	IO_FB3_MC10	bidirectional	User I/O (FB3, MC10).
40	IO_FB3_MC12	bidirectional	User I/O (FB3, MC12).
41	GND	power_in	Ground reference (0 V).
42	IO_FB3_MC16	bidirectional	User I/O (FB3, MC16).
43	IO_FB4_MC2	bidirectional	User I/O (FB4, MC2).
44	IO_FB4_MC5	bidirectional	User I/O (FB4, MC5).
45	IO_FB4_MC8	bidirectional	User I/O (FB4, MC8).
46	IO_FB4_MC3	bidirectional	User I/O (FB4, MC3).
47	IO_FB4_MC4	bidirectional	User I/O (FB4, MC4).
48	IO_FB4_MC11	bidirectional	User I/O (FB4, MC11).
49	IO_FB4_MC6	bidirectional	User I/O (FB4, MC6).
50	IO_FB4_MC14	bidirectional	User I/O (FB4, MC14).
51	IO_FB4_MC10	bidirectional	User I/O (FB4, MC10).
52	IO_FB4_MC12	bidirectional	User I/O (FB4, MC12).
53	TDO	output	IEEE 1149.1 JTAG Test Data Out. Serial data output from the boundary-scan / ISP shift register.
54	GND	power_in	Ground reference (0 V).
55	VCCIO	power_in	I/O bank supply (VCCIO). 3.0-3.6 V for 3.3 V I/O or 2.3-2.7 V for 2.5 V I/O.
56	IO_FB4_MC15	bidirectional	User I/O (FB4, MC15).
57	IO_FB4_MC17	bidirectional	User I/O (FB4, MC17).
58	IO_FB2_MC3	bidirectional	User I/O (FB2, MC3).
59	IO_FB2_MC4	bidirectional	User I/O (FB2, MC4).
60	IO_FB2_MC2	bidirectional	User I/O (FB2, MC2).
61	IO_FB2_MC5	bidirectional	User I/O (FB2, MC5).
62	IO_FB2_MC6	bidirectional	User I/O (FB2, MC6).
63	IO_FB2_MC8	bidirectional	User I/O (FB2, MC8).
64	IO_GSR_FB2_MC9	bidirectional	User I/O with global set/reset GSR alternate function (FB2, MC9). Drives the asynchronous set/reset of all macrocell registers when configured. Global control pin.

Key specifications

Parameter	Value
Manufacturer	AMD XILINX
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

Ordering variants

Same part, different packaging or reel option.

XC9572XL-10VQG64CPC44
XC9572XL-10VQG64CPCG44
XC9572XL-10VQG64CVQ44
XC9572XL-10VQG64CVQG44
XC9572XL-10VQG64CCS48
XC9572XL-10VQG64CCSG48
XC9572XL-10VQG64CVQ64
XC9572XL-10VQG64C
XC9572XL-10VQG64CTQ100
XC9572XL-10VQG64CTQG100

CAD (KiCad official)

Symbol: XC9572XL-10VQG64C
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: AMD XILINX datasheet (10 pp, sha256 658863fc1c4034b9, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF