W5500 from WIZNET, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TXN	output	TXP/TXN differential transmit signal pair to the media (Ethernet magnetics). Analog output.
2	TXP	output	TXP/TXN differential transmit signal pair to the media (Ethernet magnetics). Analog output.
3	AGND	power_in	Analog ground.
4	AVDD	power_in	Analog 3.3V power supply.
5	RXN	input	RXP/RXN differential receive signal pair from the media. Analog input.
6	RXP	input	RXP/RXN differential receive signal pair from the media. Analog input.
7	DNC	unconnected	Do Not Connect pin. Leave unconnected on the PCB.
8	AVDD	power_in	Analog 3.3V power supply.
9	AGND	power_in	Analog ground.
10	EXRES1	passive	External reference resistor pin. Connect a 12.4 kΩ, 1% resistor from this pin to analog ground (AGND) to bias internal analog circuits.
11	AVDD	power_in	Analog 3.3V power supply.
12	NC	unconnected	Not connected. Leave floating.
13	NC	unconnected	Not connected. Leave floating.
14	AGND	power_in	Analog ground.
15	AVDD	power_in	Analog 3.3V power supply.
16	AGND	power_in	Analog ground.
17	AVDD	power_in	Analog 3.3V power supply.
18	VBG	output	Band-gap output voltage; measures ~1.2V at 25°C. Must be left floating.
19	AGND	power_in	Analog ground.
20	TOCAP	passive	External reference capacitor pin. Connect a 4.7 µF capacitor to ground with a short trace to stabilize internal analog signals.
21	AVDD	power_in	Analog 3.3V power supply.
22	1V2O	power_out	1.2V internal regulator output. Must be connected to a 10 nF decoupling capacitor to ground.
23	RSVD	input	Reserved pin. Must be tied to GND. Internal pull-down.
24	SPDLED	output	Speed status LED. Low = 100 Mbps link, High = 10 Mbps link.
25	LINKLED	output	Link status LED. Low = link established, High = link not established.
26	DUPLED	output	Duplex status LED. Low = full-duplex, High = half-duplex.
27	ACTLED	output	Activity LED, driven low when carrier sense (CRS) is detected from the active PMD during TX or RX activity.
28	VDD	power_in	Digital 3.3V power supply.
29	GND	power_in	Digital ground.
30	XI/CLKIN	input	Crystal input for a 25 MHz crystal or single-ended TTL clock input (3.3V). When driven by an external clock, XO must be left unconnected.
31	XO	output	25 MHz crystal output. Float this pin if driving XI/CLKIN with an external oscillator.
32	SCSn	input	SPI chip-select (active low). Assert low to select the W5500 on the SPI bus. Internal pull-up.
33	SCLK	input	SPI clock input from the SPI master. Supports up to 80 MHz.
34	MISO	tri_state	SPI master-in / slave-out (W5500 data output). Drives data when SCSn is low; high-impedance when SCSn is high.
35	MOSI	input	SPI master-out / slave-in (W5500 data input) from the SPI master.
36	INTn	output	Interrupt output (active low). Low = interrupt asserted from W5500; High = no interrupt.
37	RSTn	input	Hardware reset input (active low). Must be held low for at least 500 µs to reset the W5500. Internal pull-up.
38	RSVD	input	Reserved pin (internal pull-down). Marked NC; leave unconnected.
39	RSVD	input	Reserved pin (internal pull-down). Marked NC; leave unconnected.
40	RSVD	input	Reserved pin (internal pull-down). Marked NC; leave unconnected.
41	RSVD	input	Reserved pin (internal pull-down). Marked NC; leave unconnected.
42	RSVD	input	Reserved pin (internal pull-down). Marked NC; leave unconnected.
43	PMODE2	input	PHY operation mode select bit 2. PMODE[2:0] selects speed/duplex and auto-negotiation configuration (e.g. 111 = all-capable auto-negotiation enabled). Internal pull-up.
44	PMODE1	input	PHY operation mode select bit 1. See PMODE[2:0] table for supported 10BT/100BT and auto-negotiation combinations. Internal pull-up.
45	PMODE0	input	PHY operation mode select bit 0. See PMODE[2:0] table for supported 10BT/100BT and auto-negotiation combinations. Internal pull-up.
46	NC	unconnected	Not connected. Leave floating.
47	NC	unconnected	Not connected. Leave floating.
48	AGND	power_in	Analog ground.

Key specifications

Parameter	Value
Manufacturer	WIZNET
Package	LQFP-48(7x7)
Category	Interface
Pins	48

CAD (KiCad official)

Symbol: W5500
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`w5500.step`	617 KB	You want the bare part, or you mark your own boards.
`w5500-etched.step`	3.5 MB	You want the part with `W5500` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 884 faces against 747 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: WIZNET datasheet (67 pp, sha256 7b826b808084ccd9, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF