W25Q32JVSSIQ
Public Unreviewedby Ray
Winbond Elec NOR FLASH, SOIC-8-208mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownW25Q32JVSSIQ
Winbond Elec · NOR FLASH · SOIC-8-208mil
W25Q32JVSSIQ from Winbond Elec, in a SOIC-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | /CS | input | SPI Chip Select input, active low. Drive low to select the device and clock instructions/data on DI/DO or IO0-IO3; drive high to deselect and place I/O pins in high impedance. Requires a valid high-to-low transition after power-up before any instruction is accepted; a pull-up to VCC is recommended. |
| 2 | DO/IO1 | bidirectional | Standard/Dual SPI serial data output (DO) driven on the falling edge of CLK. In Quad SPI mode (Quad Enable QE=1) this pin becomes bidirectional IO1 for both write and read transfers. |
| 3 | /WP/IO2 | bidirectional | Active-low Write Protect input in standard/Dual SPI mode; when asserted together with the SRP/BP/TB/SEC/CMP bits it hardware-protects part or all of the array and the Status Register. In Quad SPI mode (QE=1) this pin becomes bidirectional IO2. |
| 4 | GND | power_in | Device ground reference. Connect to the system 0 V/GND plane. |
| 5 | DI/IO0 | bidirectional | Standard/Dual SPI serial data input (DI), sampled on the rising edge of CLK for instructions, addresses and data. In Quad SPI mode this pin becomes bidirectional IO0. |
| 6 | CLK | input | SPI serial clock input. Provides the timing reference for all serial input and output operations; supports up to 133 MHz. Data on DI/IOx is latched on the rising edge; DO/IOx is updated on the falling edge. |
| 7 | /HOLD/IO3 | bidirectional | Active-low /HOLD input in standard/Dual SPI mode: while /CS is low, driving /HOLD low pauses the device (DO goes high-Z, DI/CLK are ignored) without deselecting it. In Quad SPI mode (QE=1) the pin is repurposed as bidirectional IO3. Note: on this 8-pin package the pin does NOT provide the dedicated hardware /RESET function (only SOIC-16 and TFBGA packages expose /RESET). |
| 8 | VCC | power_in | Core and I/O supply, 2.7 V to 3.6 V. Decouple with a local ceramic bypass capacitor close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Winbond Elec |
| Package | SOIC-8-208mil |
| Category | Memory |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
W25Q32JVSSIQW25Q32JVSSIQSSIGW25Q32JVSSIQSNIQW25Q32JVSSIQSNIGW25Q32JVSSIQSTIQW25Q32JVSSIQSTIGW25Q32JVSSIQZPIQW25Q32JVSSIQZPIGW25Q32JVSSIQZEIQW25Q32JVSSIQZEIGW25Q32JVSSIQXGIQW25Q32JVSSIQXGIGW25Q32JVSSIQSFIQW25Q32JVSSIQSFIGW25Q32JVSSIQDAIQW25Q32JVSSIQDAIGW25Q32JVSSIQTBIQW25Q32JVSSIQTBIGW25Q32JVSSIQTCIQW25Q32JVSSIQTCIG
CAD (KiCad official)
- Symbol:
W25Q32JVSSIQ - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8-208mil (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
w25q32jvssiq.step |
122 KB | You want the bare part, or you mark your own boards. |
w25q32jvssiq-etched.step |
2.7 MB | You want the part with W25Q32JVSSIQ already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 643 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Winbond Elec datasheet (80 pp, sha256
a835e8ae41ea71e9, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).