component
VNL5090S5TR-E
Public Unreviewedby Ray
STMicroelectronics Power Distribution Switches, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownVNL5090S5TR-E
STMicroelectronics · Power Distribution Switches · SOIC-8
VNL5090S5TR-E from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SUPPLY VOLTAGE | power_in | 5 V logic-side supply for the control section (typ. 5 V, operating range 3.5 V to 5.5 V). Powers the internal logic, driver, diagnostic and protection blocks. Decouple locally to SOURCE (GND). |
| 2 | INPUT | input | Voltage-controlled CMOS-compatible logic input with hysteresis that turns the power MOSFET ON/OFF. VIL ≤ 0.9 V, VIH ≥ 2.1 V; internally clamped. Drive through a 10 kΩ series resistor for MCU I/O protection; do not leave floating (connect to GND through 10 kΩ if unused). |
| 3 | STATUS | output | Open-drain digital diagnostic output. Pulled low (VSTAT ≤ 0.5 V at 1 mA) to signal fault/off-state open-load conditions; requires an external pull-up to the logic supply. May be left floating if unused (must not be tied directly to GND). |
| 4 | N.C. | unconnected | No internal connection. May be left floating or tied to ground; per Table 3 it is a 'do not care' pin. |
| 5 | DRAIN | power_out | Power MOSFET drain (load-side output). Internally clamped drain-source voltage ~46 V (41-52 V), RDS(on) ≈ 90 mΩ @ 25 °C, current-limited output rated for 13 A DC drain current. Pin 5 and pin 8 are the two DRAIN pins on the SO-8 and should be paralleled and tied to a copper area for heat sinking. |
| 6 | SOURCE | power_in | Power MOSFET source, also serves as the ground reference for the control section. Tie to system GND. Pins 6 and 7 are the two SOURCE pins on the SO-8 and should be paralleled on the PCB. |
| 7 | SOURCE | power_in | Power MOSFET source / ground reference for the control section. Tie to system GND. Paralleled with pin 6. |
| 8 | DRAIN | power_out | Power MOSFET drain (load-side output). Second of two DRAIN pins on the SO-8 (paralleled with pin 5) to increase current-carrying capability and improve thermal dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
VNL5090S5-EVNL5090S5TR-EVNL5090N3-EVNL5090N3TR-E
CAD (KiCad official)
- Symbol:
VNL5090S5TR-E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (None pp, sha256
d47abc67ca080985, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).