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Contents

README

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VBZA30P15

VBsemi Elec · MOSFETs · SO-8

VBZA30P15 from VBsemi Elec, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source. Tied internally to pins 2 and 3; carries continuous source current up to -13.5 A (TC = 25 °C).
2 S passive Source. Common with pins 1 and 3. Multiple source leads reduce package parasitic inductance/resistance.
3 S passive Source. Common with pins 1 and 2 for current sharing.
4 G input Gate. VGS(th) = -1.4 V to -2.5 V; absolute maximum VGS = ±20 V. Rg typ 2.2 Ω at 1 MHz; total gate charge Qg ≈ 29.5 nC at VGS = -4.5 V.
5 D passive Drain. Tied internally to pins 6, 7 and 8. VDS(max) = -30 V; RDS(on) = 11 mΩ at VGS = -10 V.
6 D passive Drain. Common with pins 5, 7 and 8. Multiple drain leads for current handling and thermal dissipation.
7 D passive Drain. Common with pins 5, 6 and 8.
8 D passive Drain. Common with pins 5, 6 and 7.

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package SO-8
Category Transistors/Thyristors
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • VBZA30P15

CAD (KiCad official)

  • Symbol: VBZA30P15
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (None pp, sha256 5abbfbb5122b226a, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF