component
USB2517I-JZX
Public Unreviewedby Ray
Microchip USB Converters, QFN-64-EP(9x9). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownUSB2517I-JZX
Microchip · USB Converters · QFN-64-EP(9x9)
USB2517I-JZX from Microchip, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | USBDN1_DM/PRT_DIS_M1 | bidirectional | Downstream port 1 USB 2.0 D- line. Also sampled at RESET_N negation as PRT_DIS_M1 strap: pull up with 10k to 3.3V to disable port 1. |
| 2 | USBDN1_DP/PRT_DIS_P1 | bidirectional | Downstream port 1 USB 2.0 D+ line. Also sampled at RESET_N negation as PRT_DIS_P1 strap. |
| 3 | USBDN2_DM/PRT_DIS_M2 | bidirectional | Downstream port 2 USB 2.0 D- line; also port-disable strap PRT_DIS_M2. |
| 4 | USBDN2_DP/PRT_DIS_P2 | bidirectional | Downstream port 2 USB 2.0 D+ line; also port-disable strap PRT_DIS_P2. |
| 5 | VDDA33 | power_in | +3.3V filtered analog PHY power, shared between adjacent ports. Requires local bypass capacitor. |
| 6 | USBDN3_DM/PRT_DIS_M3 | bidirectional | Downstream port 3 USB 2.0 D- line; also port-disable strap PRT_DIS_M3. |
| 7 | USBDN3_DP/PRT_DIS_P3 | bidirectional | Downstream port 3 USB 2.0 D+ line; also port-disable strap PRT_DIS_P3. |
| 8 | USBDN4_DM/PRT_DIS_M4 | bidirectional | Downstream port 4 USB 2.0 D- line; also port-disable strap PRT_DIS_M4. |
| 9 | USBDN4_DP/PRT_DIS_P4 | bidirectional | Downstream port 4 USB 2.0 D+ line; also port-disable strap PRT_DIS_P4. |
| 10 | VDDA33 | power_in | +3.3V filtered analog PHY power, shared between adjacent ports. |
| 11 | USBDN5_DM/PRT_DIS_M5 | bidirectional | Downstream port 5 USB 2.0 D- line; also port-disable strap PRT_DIS_M5. |
| 12 | USBDN5_DP/PRT_DIS_P5 | bidirectional | Downstream port 5 USB 2.0 D+ line; also port-disable strap PRT_DIS_P5. |
| 13 | CFG_SEL2 | input | Configuration Programming Select bit 2. Latched at rising edge of RESET_N; together with CFG_SEL[1:0] selects the hub configuration source (internal default, SMBus slave, or I2C EEPROM) per Table 5-2. |
| 14 | LED_B7_N | bidirectional | Enhanced (Amber) indicator LED output for port 7. Active low when LED support is enabled via EEPROM or SMBus. |
| 15 | LED_A7_N/PRT_SWP7 | bidirectional | Port 7 (Green) indicator LED, active low when LED support enabled. Also sampled at RESET_N negation as PRT_SWP7 strap selecting port 7 USB DP/DM electrical polarity. |
| 16 | LED_B6_N | bidirectional | Enhanced (Amber) indicator LED for port 6. |
| 17 | LED_A6_N/PRT_SWP6 | bidirectional | Port 6 (Green) indicator LED, active low when LED support enabled. Sampled at RESET_N as PRT_SWP6 strap. |
| 18 | LED_B5_N | bidirectional | Enhanced (Amber) indicator LED for port 5. |
| 19 | TEST | input | Factory test pin (XNOR continuity test of all signal pins). Input with internal weak pull-down (IPD). Tie to VSS/GND in normal operation. |
| 20 | PRTPWR4 | output | USB power enable for downstream port 4. Active-high, 12 mA drive. Drives an external high-side power switch to supply VBUS to the port. |
| 21 | OCS4_N | input | Over-current sense input for port 4 from external current monitor. Active low. Internal weak pull-up to 3.3V (IPU). |
| 22 | OCS3_N | input | Over-current sense input for port 3. Active low, internal pull-up. |
| 23 | PRTPWR3 | output | USB VBUS power enable for downstream port 3 (active high, 12 mA). |
| 24 | VDD33CR | power_in | +3.3V supply for the digital I/O and reference/input to the internal 3.3V→1.8V core regulator when enabled. |
| 25 | VDD18 | power_in | +1.8V core power. Requires a 1.0 µF (or greater) ±20% (ESR <0.1 Ω) capacitor to VSS. |
| 26 | PRTPWR2 | output | USB VBUS power enable for downstream port 2 (active high, 12 mA). |
| 27 | OCS2_N | input | Over-current sense input for port 2. Active low, internal pull-up. |
| 28 | OCS1_N | input | Over-current sense input for port 1. Active low, internal pull-up. |
| 29 | PRTPWR1 | output | USB VBUS power enable for downstream port 1 (active high, 12 mA). |
| 30 | PRTPWR5 | output | USB VBUS power enable for downstream port 5 (active high, 12 mA). |
| 31 | LED_A5_N/PRT_SWP5 | bidirectional | Port 5 (Green) indicator LED, active low when enabled. Sampled at RESET_N as PRT_SWP5 strap. |
| 32 | LED_B4_N | bidirectional | Enhanced (Amber) indicator LED for port 4. |
| 33 | LED_A4_N/PRT_SWP4 | bidirectional | Port 4 (Green) indicator LED, active low when enabled. Sampled at RESET_N as PRT_SWP4 strap. |
| 34 | LED_B3_N/GANG_EN | bidirectional | Enhanced (Amber) indicator LED for port 3 (active low when enabled). Sampled at RESET_N as GANG_EN strap: 0=individual per-port power/OCS switching, 1=ganged. |
| 35 | OCS5_N | input | Over-current sense input for port 5. Active low, internal pull-up. |
| 36 | PRTPWR7 | output | USB VBUS power enable for downstream port 7 (active high, 12 mA). |
| 37 | OCS7_N | input | Over-current sense input for port 7. Active low, internal pull-up. |
| 38 | OCS6_N | input | Over-current sense input for port 6. Active low, internal pull-up. |
| 39 | PRTPWR6 | output | USB VBUS power enable for downstream port 6 (active high, 12 mA). |
| 40 | SDA/SMBDATA/NON_REM1 | bidirectional | Serial data for I2C EEPROM interface or SMBus data (SMBDATA) - open-drain 12 mA sink with Schmitt trigger. Also sampled at RESET_N as NON_REM1 strap (with NON_REM0) to mark ports 1-3 as non-removable. |
| 41 | SCL/SMBCLK/CFG_SEL0 | bidirectional | Serial clock for I2C EEPROM (SCL) or SMBus clock (SMBCLK), open-drain 12 mA. Its logic state is latched on RESET_N rising edge as CFG_SEL0, determining the hub configuration source per Table 5-2. |
| 42 | HS_IND/CFG_SEL1 | bidirectional | Hi-Speed Upstream port indicator LED (asserted when hub is connected at HS, negated at FS). Latched on RESET_N rising edge as CFG_SEL1 per Table 5-2. |
| 43 | RESET_N | input | Active-low chip reset (Schmitt trigger). Minimum active pulse 1 µs. When tied to VDD33, the internal Power-on-Reset holds internal logic in reset until supplies are stable, so no external reset circuitry is required. |
| 44 | VBUS_DET | input | Upstream VBUS detect. Connect to the upstream port's VBUS on detachable hubs; for self-powered permanently-attached applications, tie to 3.3V or 5.0V (typically VDD33). Used to enable the upstream D+ pull-up. |
| 45 | SUSP_IND/LOCAL_PWR/NON_REM0 | bidirectional | Suspend indicator output (asserted when hub is configured and active). Also acts as LOCAL_PWR input (high=local self-power source available; low=bus-powered). Sampled at RESET_N as NON_REM0 strap (with NON_REM1) to mark ports 1-3 non-removable. |
| 46 | VDD33 | power_in | +3.3V digital I/O supply. |
| 47 | LED_A3_N/PRT_SWP3 | bidirectional | Port 3 (Green) indicator LED, active low when enabled. Sampled at RESET_N as PRT_SWP3 strap. |
| 48 | LED_B2_N/BOOST1 | bidirectional | Enhanced (Amber) indicator LED for port 2 (active low when enabled). Sampled at RESET_N as BOOST1 strap; BOOST[1:0] sets PHY drive strength for all ports (upstream and downstream) per registers F6h/F8h. |
| 49 | LED_A2_N/PRT_SWP2 | bidirectional | Port 2 (Green) indicator LED, active low when enabled. Sampled at RESET_N as PRT_SWP2 strap. |
| 50 | LED_B1_N/BOOST0 | bidirectional | Enhanced (Amber) indicator LED for port 1 (active low when enabled). Sampled at RESET_N as BOOST0 strap; BOOST[1:0] sets PHY drive level. |
| 51 | LED_A1_N/PRT_SWP1 | bidirectional | Port 1 (Green) indicator LED, active low when enabled. Sampled at RESET_N as PRT_SWP1 strap. |
| 52 | VDDA33 | power_in | +3.3V filtered analog PHY power, shared between adjacent ports. |
| 53 | USBDN6_DM/PRT_DIS_M6 | bidirectional | Downstream port 6 USB 2.0 D- line; also port-disable strap PRT_DIS_M6. |
| 54 | USBDN6_DP/PRT_DIS_P6 | bidirectional | Downstream port 6 USB 2.0 D+ line; also port-disable strap PRT_DIS_P6. |
| 55 | USBDN7_DM/PRT_DIS_M7 | bidirectional | Downstream port 7 USB 2.0 D- line; also port-disable strap PRT_DIS_M7. |
| 56 | USBDN7_DP/PRT_DIS_P7 | bidirectional | Downstream port 7 USB 2.0 D+ line; also port-disable strap PRT_DIS_P7. |
| 57 | VDDA33 | power_in | +3.3V filtered analog PHY power, shared between adjacent ports. |
| 58 | USBUP_DM | bidirectional | Upstream USB 2.0 D- line to the host or upstream hub. |
| 59 | USBUP_DP | bidirectional | Upstream USB 2.0 D+ line to the host or upstream hub. |
| 60 | XTAL2 | output | 24 MHz crystal output (other terminal of the crystal). Leave unconnected when driving XTAL1/CLKIN with an external clock. Must not drive any external circuitry other than the crystal. |
| 61 | XTAL1/CLKIN | input | 24 MHz crystal input, or external 24 MHz clock input when a crystal is not used. |
| 62 | VDD18PLL | power_in | +1.8V filtered analog power for the internal PLL. Requires a 1.0 µF (or greater) ±20% (ESR <0.1 Ω) capacitor to VSS. |
| 63 | RBIAS | passive | USB transceiver bias. Connect a 12.0 kΩ ±1% resistor from this pin to VSS/GND to set the transceiver's internal bias. |
| 64 | VDD33PLL | power_in | +3.3V PLL / regulator reference. Acts as the input to the internal 1.8V PLL regulator when that regulator is enabled. |
| 65 | VSS | power_in | Exposed thermal slug on package bottom. Must be connected to VSS/GND. Provides device ground return and thermal path to the PCB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip |
| Package | QFN-64-EP(9x9) |
| Category | Interface |
| Pins | 65 |
Ordering variants
Same part, different packaging or reel option.
USB2517I-JZX
CAD (KiCad official)
- Symbol:
USB2517I-JZX - Footprint:
Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm - 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
usb2517i-jzx.step |
359 KB | You want the bare part, or you mark your own boards. |
usb2517i-jzx-etched.step |
3.1 MB | You want the part with USB2517I-JZX already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 812 faces against 398 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip datasheet (59 pp, sha256
fd9caf7754e56560, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).