USB2517-JZX from Microchip, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	USBDN1_DM/PRT_DIS_M1	bidirectional	Downstream Port 1 USB 2.0 D- (Hi-Speed differential). Doubles as PRT_DIS_M1 port-disable strap sampled at RESET_N deassertion when strap option is enabled.
2	USBDN1_DP/PRT_DIS_P1	bidirectional	Downstream Port 1 USB 2.0 D+ (Hi-Speed differential). Doubles as PRT_DIS_P1 port-disable strap sampled at RESET_N deassertion.
3	USBDN2_DM/PRT_DIS_M2	bidirectional	Downstream Port 2 USB 2.0 D-. Doubles as PRT_DIS_M2 port-disable strap.
4	USBDN2_DP/PRT_DIS_P2	bidirectional	Downstream Port 2 USB 2.0 D+. Doubles as PRT_DIS_P2 port-disable strap.
5	VDDA33	power_in	+3.3V filtered analog PHY power, shared between adjacent downstream ports.
6	USBDN3_DM/PRT_DIS_M3	bidirectional	Downstream Port 3 USB 2.0 D-. Doubles as PRT_DIS_M3 port-disable strap.
7	USBDN3_DP/PRT_DIS_P3	bidirectional	Downstream Port 3 USB 2.0 D+. Doubles as PRT_DIS_P3 port-disable strap.
8	USBDN4_DM/PRT_DIS_M4	bidirectional	Downstream Port 4 USB 2.0 D-. Doubles as PRT_DIS_M4 port-disable strap.
9	USBDN4_DP/PRT_DIS_P4	bidirectional	Downstream Port 4 USB 2.0 D+. Doubles as PRT_DIS_P4 port-disable strap.
10	VDDA33	power_in	+3.3V filtered analog PHY power, shared between adjacent downstream ports.
11	USBDN5_DM/PRT_DIS_M5	bidirectional	Downstream Port 5 USB 2.0 D-. Doubles as PRT_DIS_M5 port-disable strap.
12	USBDN5_DP/PRT_DIS_P5	bidirectional	Downstream Port 5 USB 2.0 D+. Doubles as PRT_DIS_P5 port-disable strap.
13	CFG_SEL2	input	Configuration Programming Select bit 2. Latched at RESET_N rising edge with CFG_SEL1/CFG_SEL0 to select hub configuration method (internal default / SMBus slave / I2C EEPROM / strap variants) per Table 5-2.
14	LED_B7_N	bidirectional	Enhanced (amber) indicator LED for downstream port 7. Active low when LED support is enabled via EEPROM/SMBus. 12 mA I/O buffer.
15	LED_A7_N/PRT_SWP7	bidirectional	Port 7 primary (green) LED indicator, active low when LED support is enabled. Doubles as PRT_SWP7 strap: sampled at RESET_N deassertion to swap D+/D- polarity of downstream port 7.
16	LED_B6_N	bidirectional	Enhanced (amber) indicator LED for downstream port 6. Active low when LED support is enabled.
17	LED_A6_N/PRT_SWP6	bidirectional	Port 6 primary (green) LED indicator. Doubles as PRT_SWP6 D+/D- polarity swap strap for downstream port 6.
18	LED_B5_N	bidirectional	Enhanced (amber) indicator LED for downstream port 5. Active low when LED support is enabled.
19	TEST	input	Manufacturing test pin (IPD, internal weak pull-down). Enables XNOR continuity test of all signal pins; tie low or leave open in normal operation.
20	PRTPWR4	output	Port 4 power enable output (active-high, 12 mA drive). Drives an external high-side power switch to supply VBUS to the downstream USB port.
21	OCS4_N	input	Port 4 over-current sense input, active-low, from external current monitor. Internal weak pull-up to 3.3V.
22	OCS3_N	input	Port 3 over-current sense input, active-low. Internal weak pull-up to 3.3V.
23	PRTPWR3	output	Port 3 power enable output (active-high, 12 mA drive).
24	VDD33CR	power_in	+3.3V supply for digital I/O and core regulator reference. When the internal 1.8V core regulator is enabled, this pin is its regulator input.
25	VDD18	power_in	+1.8V core power. Requires a 1.0 uF (or greater) +/-20% (ESR <0.1 ohm) capacitor to VSS.
26	PRTPWR2	output	Port 2 power enable output (active-high, 12 mA drive).
27	OCS2_N	input	Port 2 over-current sense input, active-low. Internal weak pull-up to 3.3V.
28	OCS1_N	input	Port 1 over-current sense input, active-low. Internal weak pull-up to 3.3V.
29	PRTPWR1	output	Port 1 power enable output (active-high, 12 mA drive).
30	PRTPWR5	output	Port 5 power enable output (active-high, 12 mA drive).
31	LED_A5_N/PRT_SWP5	bidirectional	Port 5 primary (green) LED indicator. Doubles as PRT_SWP5 D+/D- polarity swap strap for downstream port 5.
32	LED_B4_N	bidirectional	Enhanced (amber) indicator LED for downstream port 4. Active low when LED support is enabled.
33	LED_A4_N/PRT_SWP4	bidirectional	Port 4 primary (green) LED indicator. Doubles as PRT_SWP4 D+/D- polarity swap strap for downstream port 4.
34	LED_B3_N/GANG_EN	bidirectional	Enhanced (amber) LED for port 3 when LED support is enabled. Doubles as GANG_EN strap sampled at RESET_N deassertion: 0 = individual per-port power/OCS sensing (LED active high); 1 = ganged power/OCS sensing (LED active low).
35	OCS5_N	input	Port 5 over-current sense input, active-low. Internal weak pull-up to 3.3V.
36	PRTPWR7	output	Port 7 power enable output (active-high, 12 mA drive).
37	OCS7_N	input	Port 7 over-current sense input, active-low. Internal weak pull-up to 3.3V.
38	OCS6_N	input	Port 6 over-current sense input, active-low. Internal weak pull-up to 3.3V.
39	PRTPWR6	output	Port 6 power enable output (active-high, 12 mA drive).
40	SDA/SMBDATA/NON_REM1	bidirectional	I2C serial data / SMBus data (open-drain, 12 mA sink, Schmitt trigger; meets I2C-Bus v2.1). Doubles as NON_REM1 strap (with NON_REM0) sampled at RESET_N deassertion to mark ports [3:1] non-removable.
41	SCL/SMBCLK/CFG_SEL0	bidirectional	I2C serial clock / SMBus clock (open-drain, 12 mA sink, Schmitt trigger). Also CFG_SEL0: latched on RESET_N rising edge to select hub configuration method per Table 5-2.
42	HS_IND/CFG_SEL1	bidirectional	Hi-Speed upstream connection indicator LED (asserted = HS, negated = FS); polarity set by CFG_SEL1. Also CFG_SEL1 configuration select bit latched on RESET_N rising edge per Table 5-2.
43	RESET_N	input	Active-low reset input (Schmitt trigger). Minimum active-low pulse 1 us. When tied to VDD33, the internal POR is used and no external reset circuit is required.
44	VBUS_DET	input	Detects upstream VBUS power to signal a connect event by asserting the internal D+ pull-up. Connect to the upstream port VBUS for detachable hubs, or to 3.3V/5V (typically VDD33) for self-powered permanently attached applications.
45	SUSP_IND/LOCAL_PWR/NON_REM0	bidirectional	Suspend indicator LED (asserted = hub configured/active, negated = unconfigured or USB suspend). Also LOCAL_PWR input: high = local self-power available, low = bus powered. Also NON_REM0 strap latched at RESET_N deassertion (with NON_REM1) to mark ports [3:1] non-removable.
46	VDD33	power_in	+3.3V digital I/O power.
47	LED_A3_N/PRT_SWP3	bidirectional	Port 3 primary (green) LED indicator. Doubles as PRT_SWP3 D+/D- polarity swap strap for downstream port 3.
48	LED_B2_N/BOOST1	bidirectional	Enhanced (amber) LED for port 2 when LED support is enabled. Also BOOST1 strap latched at RESET_N deassertion (with BOOST0) to select PHY drive-strength boost level for all upstream/downstream ports.
49	LED_A2_N/PRT_SWP2	bidirectional	Port 2 primary (green) LED indicator. Doubles as PRT_SWP2 D+/D- polarity swap strap for downstream port 2.
50	LED_B1_N/BOOST0	bidirectional	Enhanced (amber) LED for port 1 when LED support is enabled. Also BOOST0 strap latched at RESET_N deassertion (with BOOST1) to select PHY drive-strength boost.
51	LED_A1_N/PRT_SWP1	bidirectional	Port 1 primary (green) LED indicator. Doubles as PRT_SWP1 D+/D- polarity swap strap for downstream port 1.
52	VDDA33	power_in	+3.3V filtered analog PHY power, shared between adjacent downstream ports.
53	USBDN6_DM/PRT_DIS_M6	bidirectional	Downstream Port 6 USB 2.0 D-. Doubles as PRT_DIS_M6 port-disable strap.
54	USBDN6_DP/PRT_DIS_P6	bidirectional	Downstream Port 6 USB 2.0 D+. Doubles as PRT_DIS_P6 port-disable strap.
55	USBDN7_DM/PRT_DIS_M7	bidirectional	Downstream Port 7 USB 2.0 D-. Doubles as PRT_DIS_M7 port-disable strap.
56	USBDN7_DP/PRT_DIS_P7	bidirectional	Downstream Port 7 USB 2.0 D+. Doubles as PRT_DIS_P7 port-disable strap.
57	VDDA33	power_in	+3.3V filtered analog PHY power, shared between adjacent downstream ports.
58	USBUP_DM	bidirectional	Upstream USB 2.0 D- (to host or upstream hub). Analog IO-U buffer defined by USB specification.
59	USBUP_DP	bidirectional	Upstream USB 2.0 D+ (to host or upstream hub). Analog IO-U buffer.
60	XTAL2	output	24 MHz crystal output. Connect to the other terminal of the crystal; leave as NC when an external clock drives XTAL1/CLKIN. Must not drive any external circuit beyond the crystal.
61	XTAL1/CLKIN	input	24 MHz crystal input, or single-ended external 24 MHz clock input when no crystal is used.
62	VDD18PLL	power_in	+1.8V filtered analog power for internal PLL. Requires 1.0 uF (or greater) +/-20% (ESR <0.1 ohm) capacitor to VSS.
63	RBIAS	passive	USB transceiver bias resistor. Connect a 12.0k ohm +/-1% resistor from this pin to ground to set the transceiver's internal bias.
64	VDD33PLL	power_in	+3.3V PLL regulator reference / digital I/O supply. When the internal PLL 1.8V regulator is enabled, this pin is its regulator input.
65	VSS	power_in	Exposed thermal slug on package bottom. Must be connected to VSS/GND for both electrical ground return and thermal dissipation.

Key specifications

Parameter	Value
Manufacturer	Microchip
Package	QFN-64-EP(9x9)
Category	Interface
Pins	65

Ordering variants

Same part, different packaging or reel option.

USB2517-JZX

CAD (KiCad official)

Symbol: USB2517-JZX
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`usb2517-jzx.step`	359 KB	You want the bare part, or you mark your own boards.
`usb2517-jzx-etched.step`	3.0 MB	You want the part with `USB2517-JZX` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 785 faces against 398 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip datasheet (59 pp, sha256 de3a58b7966803c9, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF