component
UCC28C45DR
Public Unreviewedby Ray
Texas Instruments TI Switching Controllers, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUCC28C45DR
Texas Instruments TI · Switching Controllers · SOIC-8
UCC28C45DR from Texas Instruments TI, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error-amplifier output for loop compensation. Also used as a control port for opto-isolated secondary-side feedback; internally current-limited so pulling COMP to GND forces zero duty cycle. VOH ≈ VREF−0.2 V; VOL ≈ 0.1 V (typ). |
| 2 | FB | input | Inverting input to the internal error amplifier. Non-inverting input is trimmed internally to 2.5 V ±1%; drive FB from the converter output feedback divider to close the voltage loop. |
| 3 | CS | input | Primary-side current-sense input to the PWM comparator (non-inverting). Connect to a current-sense resistor; the PWM comparator terminates OUT when CS exceeds the COMP-derived threshold (COMP-to-CS offset ≈ 1.15 V, current-sense gain ≈ 3 V/V). Max input signal 1 V typ. |
| 4 | RT/CT | bidirectional | Oscillator timing pin. Connect timing resistor RRT from VREF to this pin and timing capacitor CCT from this pin to GND to set the fixed oscillator frequency. Discharge current is trimmed (~8.4 mA typ) for precise deadtime and duty-cycle programming. For UCC28C45, the OUT switching frequency is fOSC/2. |
| 5 | GND | power_in | Common ground return for the output driver stage and the logic/analog control section. All device voltages are referenced to this pin. |
| 6 | OUT | output | Totem-pole gate-drive output intended to directly drive an external MOSFET. Peak source/sink capability ±1 A (200 mA continuous), rise/fall ~25 ns / 20 ns into 1 nF. For UCC28C45 an internal T flip-flop halves the oscillator frequency, limiting maximum duty cycle to <50%. OUT is actively held low when VDD is below the UVLO turn-on threshold. |
| 7 | VDD | power_in | Analog controller bias supply. Recommended operating range up to 18 V (abs max 20 V). UCC28C45 UVLO: VDDON ≈ 8.4 V, VDDOFF ≈ 7.6 V. Bypass to GND with a 0.1 µF ceramic close to the pin plus bulk capacitance at least 10× the driven MOSFET gate capacitance. Start-up current 50 µA typ; operating current 2.3 mA typ. |
| 8 | VREF | power_out | 5 V ±1% precision reference output used to source the RT/CT timing-resistor current and drive light external loads (up to 20 mA source). Bypass to GND with ≥0.1 µF ceramic placed close to the pin; additional bypassing required if driving external loads. Short-circuit protected (~45 mA typ). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments TI |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
UCC28C45DRDUCC28C45DRUCC28C45DRDGKUCC28C45DRDGKR
CAD (KiCad official)
- Symbol:
UCC28C45DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments TI datasheet (60 pp, sha256
9fa55f996731c56b, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).