component
ucc28c44dr
Public Unreviewedby Ray
Texas Instruments AC-DC Controllers and Regulators, SOIC-8-150mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownUCC28C44DR
Texas Instruments · AC-DC Controllers and Regulators · SOIC-8-150mil
UCC28C44DR from Texas Instruments, in a SOIC-8-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for loop compensation. Also commonly used as a control port with a secondary-side error amplifier and opto-isolator. The internal error amp is current limited (~1mA source) so external clamping of COMP to GND commands zero duty cycle. |
| 2 | FB | input | Inverting input of the internal error amplifier used to close the voltage-feedback loop. The non-inverting input is internally biased to a trimmed 2.5V ±1% reference. |
| 3 | CS | input | Primary-side current sense input; non-inverting input of the PWM comparator. Connect to the current-sense resistor; the internal comparator terminates the OUT pulse when CS exceeds the (level-shifted) COMP signal. Can also accept a ramp for voltage-mode control. Absolute range −0.3V to 6.3V. |
| 4 | RT/CT | bidirectional | Fixed-frequency oscillator timing pin. Connect a timing resistor (RRT) from this pin to VREF and a timing capacitor (CCT) from this pin to GND to set fOSC. On the UCC28C44, the OUT switching frequency (fSW) equals fOSC/2 due to the internal T flip-flop. |
| 5 | GND | power_in | Common ground return for both the output driver stage and the logic/control section (single-ground 8-pin device). Keep timing-capacitor and bypass returns short and directly to this pin. |
| 6 | OUT | output | High-current totem-pole gate driver output intended to drive an external MOSFET directly. Peak source/sink current ±1A with ~25ns rise / ~20ns fall. On the UCC28C44 the output runs at fOSC/2 with maximum duty cycle limited to <50%. Held actively low while VDD is below the UVLO turn-on threshold. |
| 7 | VDD | power_in | Analog controller bias supply. Absolute maximum 20V; recommended operating maximum 18V. UVLO turn-on 8.4V / turn-off 7.6V for this UCC28C44 (DC/DC) variant. Requires a 0.1µF ceramic bypass to GND with minimal trace length plus additional bulk capacitance ≥10× the driven MOSFET's gate capacitance. |
| 8 | VREF | power_out | 5V ±1% trimmed reference output used to bias the RT/CT timing network and light external loads (source up to 20mA recommended, ~45mA short-circuit typ). Requires a ceramic bypass capacitor ≥0.1µF close to the pin for stability; add extra bypass if driving external loads. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8-150mil |
| Category | PMIC |
| Pins | 8 |
Ordering variants
UCC28C44DRDUCC28C44DRDRUCC28C44DRDR.AUCC28C44DRDGKUCC28C44DRDGKRUCC28C44DRDGKR.AUCC28C44DRDGKRG4
CAD (KiCad official)
- Symbol:
UCC28C44DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8-150mil (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (None pp, sha256
9fa55f996731c56b, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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