component
ucc28c42dr
Public Unreviewedby Ray
Texas Instruments DC-DC Converters, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownUCC28C42DR
Texas Instruments · DC-DC Converters · SOIC-8
UCC28C42DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for loop compensation. Also usable as a control port via an opto-isolator from a secondary-side error amplifier. Internally current-limited; forcing COMP to GND commands zero duty cycle. |
| 2 | FB | input | Inverting input of the internal error amplifier used to close the power converter voltage-feedback loop. The non-inverting input is internally trimmed to 2.5V ±1%. |
| 3 | CS | input | Primary-side current sense pin; non-inverting input to the PWM comparator. Connect to the current-sensing resistor; the PWM terminates the OUT switch conduction when CS exceeds the scaled error-amplifier signal. Can also be driven by a voltage ramp for voltage-mode operation. |
| 4 | RT/CT | bidirectional | Fixed-frequency oscillator set point. Connect RRT to VREF and CCT to GND to set fSW. For UCC28C42, gate-drive fSW equals fOSC. Keep CCT lead to GND short; a separate ground trace for CCT is recommended. |
| 5 | GND | power_in | Ground return for the output driver stage and the logic-level controller section. All voltages in the datasheet are referenced to this pin. |
| 6 | OUT | output | Gate-drive output of the on-chip rail-to-rail driver, intended to directly drive an external MOSFET. Sources and sinks up to ±1A peak (25ns rise / 20ns fall). Runs at fOSC and can operate near 100% duty cycle on the UCC28C42; held actively low when VDD is below the turn-on threshold. |
| 7 | VDD | power_in | Analog controller bias input; supplies the whole device. UVLO turn-on 14.5V, turn-off 9V. Absolute max 20V; recommended max 18V. Bypass with 0.1µF directly to GND, plus additional capacitance ≥10× the driven FET's gate capacitance. |
| 8 | VREF | power_out | 5V ±1% internal reference output (typ 5V, 4.9-5.1V at TJ=25°C). Used to charge the oscillator timing capacitor through RRT and to bias external circuitry (≤20mA source). Bypass to GND with ≥0.1µF ceramic close to the pin. Short-circuit source current 30-55mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
UCC28C42DRDUCC28C42DRUCC28C42DRDGKUCC28C42DRDGKR
CAD (KiCad official)
- Symbol:
UCC28C42DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (None pp, sha256
9fa55f996731c56b, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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