UCC28063DR from Texas Instruments, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ZCDB	input	Zero Current Detection Input for Channel B. Senses the boost inductor demagnetization via an auxiliary winding to trigger the next switching cycle in transition mode. Absolute max input range -0.5 V to 4 V, ±5 mA continuous input current.
2	VSENSE	input	Output DC voltage sense input. Connects through a resistor divider from the boost output to the voltage feedback loop and OVP comparators. Absolute max -0.5 V to 7 V.
3	TSET	input	Timing set input. A resistor to AGND programs the internal maximum on-time (frequency clamp) for transition-mode operation.
4	PHB	input	Phase-B enable/disable input for phase management. Allows disabling Channel B at light loads to improve light-load efficiency.
5	COMP	output	Error amplifier output / voltage-loop compensation node. External RC network to AGND sets loop bandwidth. Absolute max -0.5 V to 7 V; internally clamped in normal operation.
6	AGND	power_in	Analog ground reference for all low-level control signals (VSENSE, COMP, TSET, VREF, CS, VINAC, HVSEN). Should be a quiet star point separated from PGND.
7	VINAC	input	Input AC voltage sense. Scaled rectified line voltage input used for brownout/dropout detection and current-shaping reference. Absolute max -0.5 V to 7 V.
8	HVSEN	input	High-voltage output sense input for the redundant fail-safe overvoltage protection (FailSafe OVP). Independent divider from the boost output prevents catastrophic failure if the primary VSENSE divider opens. Absolute max -0.5 V to 7 V.
9	PWMCNTL	output	PWM-Control output. Open-drain-style status output to signal downstream converters (e.g. Power Good). Absolute max -0.5 V to 20 V, 10 mA continuous.
10	CS	input	Current sense input. Senses the combined boost switch/inductor current through a sense resistor for cycle-by-cycle peak current limiting. Absolute max -0.5 V to 3 V, peak input current -30 mA.
11	GDB	output	Channel B gate drive output. 1 A source / 1.8 A sink capability for driving an external boost MOSFET gate. Absolute max -0.5 V to VCC+0.3 V, ±25 mA continuous.
12	VCC	power_in	Bias supply input. Powers the internal control circuitry and gate drivers. Internally clamped; absolute max 21 V, 20 mA continuous input current.
13	PGND	power_in	Power ground return for the gate driver output stages (GDA/GDB). Should be tied to AGND at a single star point close to the IC.
14	GDA	output	Channel A gate drive output. 1 A source / 1.8 A sink capability for driving an external boost MOSFET gate. Absolute max -0.5 V to VCC+0.3 V, ±25 mA continuous.
15	VREF	power_out	Internal voltage reference output. Provides a regulated bias for external divider networks; output current limited to -10 mA.
16	ZCDA	input	Zero Current Detection Input for Channel A. Senses the boost inductor demagnetization via an auxiliary winding to trigger the next switching cycle in transition mode. Absolute max input range -0.5 V to 4 V, ±5 mA continuous input current.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOP-16
Category	PMIC
Pins	16

Ordering variants

Same part, different packaging or reel option.

UCC28063DR
UCC28063DRD

CAD (KiCad official)

Symbol: UCC28063DR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (47 pp, sha256 228d8fb28ab79947, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF