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Contents

README

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UC3844BDTR

XBLW · AC-DC Controllers and Regulators · SOP-8

UC3844BDTR from XBLW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COMP output Error amplifier output / compensation node. External R-C network from COMP to VFB sets the loop compensation. Pulling COMP within two diode drops of GND shuts the output off.
2 VFB input Inverting input of the internal error amplifier. Normally tied via a resistor divider to the converter output; internal reference on the non-inverting input is 2.5 V.
3 ISENSE input Current-sense input for peak primary current control. Peak current threshold IS(MAX) ≈ 1.0 V / Rs; input voltage gain 3 V/V (typ). Raising this pin above 1 V terminates the output pulse (also used for shutdown).
4 RT/CT passive Oscillator timing pin. External RT to VREF (pin 8) and CT to GND (pin 5) set the oscillator frequency, f ≈ 1.8 / (RT·CT) for RT > 5 kΩ. Oscillator swing ~1.6 Vpp.
5 GND power_in Device ground (signal and power return). Timing/bypass caps must be returned to this pin and single-point grounded.
6 OUTPUT output Totem-pole (push-pull) gate-drive output, capable of ±1 A peak. Drives external power MOSFET gates directly; typical VOH ≈ 13 V, VOL ≈ 0.1 V at 20 mA. Rise/fall time ~50 ns into 1 nF.
7 VCC power_in Chip supply. UVLO turn-on threshold 15.5 V typ, turn-off 9.8 V typ (hysteretic for bootstrap start-up). Absolute max 30 V, internally clamped by a 34 V zener; operating current ~11 mA, startup ~0.26 mA.
8 VREF power_out Buffered 5.0 V reference output (4.9-5.1 V), used to bias the oscillator timing resistor and external circuitry. Short-circuit current limited to ~80 mA.

Key specifications

Parameter Value
Manufacturer XBLW
Package SOP-8
Category PMIC
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • UC3844BDTR
  • UC3844BDTRAN

CAD (KiCad official)

  • Symbol: UC3844BDTR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
uc3844bdtr.step 122 KB You want the bare part, or you mark your own boards.
uc3844bdtr-etched.step 2.3 MB You want the part with UC3844BDTR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 567 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XBLW datasheet (13 pp, sha256 d938ec712fc51657, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF