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Contents

README

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TX5818

XDS · Battery Management · QFN-16(3x3)

TX5818 from XDS, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VSYS power_out Boost/system output pin. In 2S/5V mode this is the boosted system rail feeding the battery through the internal switch node; connect to the SW inductor / boost output filter cap.
2 SW passive Switch node of the internal power stage. Connect to the 2.2µH inductor for the boost (5V input) or buck (9V input) converter.
3 SW passive Switch node of the internal power stage (paralleled with pin 2). Connect to the 2.2µH switching inductor.
4 PGND power_in Power ground. Return path for the switching power stage; tie to the ground plane together with pins 5, 17 (thermal pad) and the input/output capacitor grounds.
5 PGND power_in Power ground (paralleled with pins 4 and 17 thermal pad).
6 FV_SEL input Full-charge voltage select. Float or tie to GND through 10kΩ: 2S = 8.4V, 3S = 12.6V. Tie to VLDO through 10kΩ: 2S = 8.7V, 3S = 13.05V.
7 VIN power_in Power input pin. Absolute max 26V; operating 4.4V-7V (5V adapter mode) or 8.4V-10.8V (9V adapter mode). OVP threshold typ. 7V (5V mode) or 10.8V (9V mode). Decouple with a 22µF x2 input capacitor.
8 EN input Chip enable pin, active high. Drive high to enable the charger.
9 VLDO power_out Internal LDO output, typ. 4.80V. Used as pull-up reference for FV_SEL / CELL / NTC configuration resistors; decouple with a small ceramic cap to GND.
10 LED output Charge status indicator drive pin. Sinks current through an external LED: LED on during charging, off when charge is complete.
11 CELL input Cell count select. Float or tie to GND through 10kΩ = 2S (two-cell) charge mode; tie to VLDO through 10kΩ = 3S (three-cell) charge mode.
12 AGND power_in Analog ground. Star-connect to PGND at a single point near the IC to keep switching return currents out of the analog reference.
13 NC unconnected No-connect. Must be left floating; do not tie to any rail or ground.
14 NTC input Battery temperature sense input. Connect a fixed resistor to VLDO and an NTC thermistor (placed near the battery) to GND to form a divider. Leave floating if NTC protection is not used.
15 ISET output Charge current programming pin. Sets ICHG via external resistor RSET to GND; VISET typ. 1.19V. Examples: RSET=2kΩ→1.55A, 3kΩ→1.05A, 5.1kΩ→0.62A, 10kΩ→0.31A (5V input, 2S).
16 BATT power_out Battery positive terminal connection. Drives the 2S or 3S Li-ion battery stack; decouple locally with a 22µF ceramic and 0.1µF.
17 PGND power_in Exposed thermal pad on the package bottom, electrically PGND. Must be soldered to the PCB ground copper for both electrical return and heat dissipation.

Key specifications

Parameter Value
Manufacturer XDS
Package QFN-16(3x3)
Category PMIC
Pins 17

Ordering variants

Same part, different packaging or reel option.

  • TX5818 (QFN3X3-16)
  • TX5818 (ESOP16)

CAD (KiCad official)

  • Symbol: TX5818
  • Footprint: Package_DFN_QFN:MPS_QFN-16_3x3mm_P0.5mm
  • 3D model: QFN-16(3x3) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XDS datasheet (12 pp, sha256 a029ed86586d71df, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF