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Contents

README

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TX4139

XDS · DC-DC Converters · SOIC-8-EP

TX4139 from XDS, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW output Switch node output; source of the internal high-side power MOSFET. Connects to the external inductor and the cathode of the freewheeling Schottky diode. Voltage swings between roughly GND (via diode) and VIN at the 200 kHz switching frequency; absolute rating -0.3 V to VIN + 0.3 V.
2 ILIM power_in Programmable maximum-peak-current sense pin. Connect an external precision sense resistor between ILIM and VIN; the internal power current flows through this resistor, and the resulting voltage drop sets the cycle-by-cycle current limit (typical values 30 mΩ for 2 A, 40 mΩ for 1 A, 50 mΩ for 0.8 A). Pin 2 and pin 9 are internally connected.
3 VIN power_in Main supply input, 4.5 V to 75 V (absolute max 76 V). Internally connects to the drain of the high-side power MOSFET and supplies the whole chip. Requires a low-ESR input capacitor (47 µF-100 µF electrolytic plus a 0.1 µF ceramic) placed as close as possible to reduce switching spikes.
4 GND power_in Device ground and voltage reference for the regulated output. Should be routed with a quiet ground return, kept outside the D1-to-CIN high-di/dt loop to avoid coupling switching noise into the feedback.
5 FB input Feedback input, regulated to the internal 0.805 V (typ) bandgap reference. Set VOUT with an external divider using R1 ≈ 300 kΩ and R2 = R1 / (VOUT/0.805 − 1). When VFB falls below ~250 mV the oscillator frequency folds back (to ~70 kHz) to protect against short-circuit current runaway. Bias current is ~10 nA.
6 EN input Enable input. Pulling this pin low disables (shuts down) the chip; leaving it floating enables normal operation. Absolute maximum rating -0.3 V to +6.5 V - do not tie directly to VIN when VIN > 6.5 V.
7 POK output Power-good open-drain output. Pulled low when the FB voltage is less than 90 % of 0.8 V (i.e. below ~0.72 V); high-impedance when the output is in regulation. Requires an external pull-up (to system rail or the regulated output) to be observed; may be tied to GND or left floating if unused. Absolute maximum on POK is 0 V to 45 V.
8 BS passive Bootstrap capacitor pin; supplies the positive rail (VBST − VSW ≈ 6 V typ) for the high-side MOSFET gate driver. Connect a 100 nF ceramic capacitor (with a series ~10 Ω resistor per the reference schematic) between BS and SW. Absolute maximum VBST = VSW + 6.0 V.
9 ILIM power_in Exposed thermal pad on the ESOIC-8 package, internally connected to the ILIM node (same net as pin 2). Provides the primary heat-sink path for the internal power MOSFET and must be soldered to a copper thermal pad and connected to the sense resistor / VIN side network with pin 2.

Key specifications

Parameter Value
Manufacturer XDS
Package SOIC-8-EP
Category PMIC
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • TX4139

CAD (KiCad official)

  • Symbol: TX4139
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tx4139.step 125 KB You want the bare part, or you mark your own boards.
tx4139-etched.step 1.4 MB You want the part with TX4139 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 354 faces against 152 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XDS datasheet (8 pp, sha256 267c7bcc1bd5573b, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF