TUSB1210BRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	REFCLK	input	Reference clock input (square-wave only), 3.3 V level. Tie to GND when CLOCK (pin 26) is configured as Input Mode. Connect to a 3-3.6 V square-wave reference in Output Mode; frequency is selected by CFG (19.2 or 26 MHz).
2	NXT	output	ULPI NXT output signal referenced to VDDIO. Indicates to the link that the PHY is ready to accept or provide data on the next clock edge.
3	DATA0	bidirectional	ULPI DATA bit 0, synchronized to CLOCK; VDDIO logic levels.
4	DATA1	bidirectional	ULPI DATA bit 1, synchronized to CLOCK; VDDIO logic levels.
5	DATA2	bidirectional	ULPI DATA bit 2, synchronized to CLOCK; VDDIO logic levels.
6	DATA3	bidirectional	ULPI DATA bit 3, synchronized to CLOCK; VDDIO logic levels.
7	DATA4	bidirectional	ULPI DATA bit 4, synchronized to CLOCK; VDDIO logic levels.
8	N/C	unconnected	No connection.
9	DATA5	bidirectional	ULPI DATA bit 5, synchronized to CLOCK; VDDIO logic levels.
10	DATA6	bidirectional	ULPI DATA bit 6, synchronized to CLOCK; VDDIO logic levels.
11	CS	input	Active-high chip select, VDDIO level. When low, the IC is powered down and the ULPI bus is tri-stated; when high, normal operation. Tie to VDDIO if unused.
12	VDD15	power_out	1.5 V internal LDO output. Connect to an external filtering capacitor; do not load externally.
13	DATA7	bidirectional	ULPI DATA bit 7, synchronized to CLOCK; VDDIO logic levels.
14	CFG	input	REFCLK frequency configuration pin, VDDIO level. 0 selects 19.2 MHz REFCLK; 1 selects 26 MHz REFCLK.
15	N/C	unconnected	No connection.
16	N/C	unconnected	No connection.
17	CPEN	output	CMOS active-high digital output for controlling an external 5 V VBUS supply (charge pump enable). VDD33 level; VOH ≥ VDD33 - 0.3 V at IOH = -3 mA, VOL ≤ 0.3 V at IOL = 3 mA.
18	DP	bidirectional	USB D+ analog I/O to the USB connector. Internal 5 V short-circuit protection to VBUS. Referenced to VDD33.
19	DM	bidirectional	USB D- analog I/O to the USB connector. Internal 5 V short-circuit protection to VBUS. Referenced to VDD33.
20	VDD33	power_out	3.3 V internal LDO output. Connect to an external filtering capacitor; do not load externally.
21	VBAT	power_in	Main input supply / battery source. Recommended 2.7-4.8 V (3.15 V min for USB 2.0 certification with VDD33 supplied internally). Absolute max 5 V (5.5 V transient ≤5 ms cumulative).
22	VBUS	input	VBUS pin from the USB connector, sensed by the OTG session/voltage comparators. Protected over -2 V to 20 V range.
23	ID	bidirectional	Identification (ID) pin of the USB OTG connector. Analog I/O referenced to VDD33 with internal 5 V short-circuit protection.
24	N/C	unconnected	No connection.
25	N/C	unconnected	No connection.
26	CLOCK	bidirectional	ULPI 60 MHz clock on which ULPI data is synchronized; VDDIO level. Input Mode (default): CLOCK is driven by the link. Output Mode: after 4 rising edges are detected on REFCLK, CLOCK becomes a 60 MHz output.
27	RESETB	input	Active-low reset input, VDDIO level. When low, all digital logic (except the 32 kHz power-up sequencing logic) and registers are reset to defaults and the ULPI bus is tri-stated. Minimum external pulse width 8 CLOCK cycles when CLOCK is toggling.
28	VDD18	power_in	External 1.8 V supply input. Connect to an external filtering capacitor. Both VDD18 pins (28 and 30) must be tied to the same 1.8 V rail.
29	STP	input	ULPI STP input signal from the link, VDDIO level. Asserted by the link to stop the data stream on the bus.
30	VDD18	power_in	External 1.8 V supply input (second pin, tie together with pin 28). Connect to an external filtering capacitor.
31	DIR	output	ULPI DIR output signal, VDDIO level. Indicates the direction of ULPI data (PHY-to-link or link-to-PHY) on the DATA[7:0] bus.
32	VDDIO	power_in	External 1.8 V supply input for digital I/Os (ULPI-side logic level). Operating range 1.71-1.98 V. Connect to an external filtering capacitor.
33	GND	power_in	Thermal pad - reference ground. Must be soldered to the PCB ground plane for both electrical return and thermal dissipation.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32-EP(5x5)
Category	Interface
Pins	33

Ordering variants

Same part, different packaging or reel option.

TUSB1210BRHBR
TUSB1210BRHBRRHBT

CAD (KiCad official)

Symbol: TUSB1210BRHBR
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (73 pp, sha256 9baf26d43a79f3fd, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF