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TRS3122ERGER

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by Ray

Texas Instruments RS232 ICs, VQFN-24-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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TRS3122ERGER

Texas Instruments · RS232 ICs · VQFN-24-EP(4x4)

TRS3122ERGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 C3+ passive Positive terminal of the voltage-tripler charge-pump capacitor. Not needed for VCC 3 V to 5.5 V (doubler mode). Connect a 0.1 uF flying capacitor between C3+ and C3-.
2 C3- passive Negative terminal of the voltage-tripler charge-pump capacitor. Not needed for VCC 3 V to 5.5 V. Pair with C3+ via a 0.1 uF flying capacitor.
3 RIN1 input RS-232 receiver 1 input. Accepts +/-15 V RS-232 line levels; typical input resistance 3-7 kohm.
4 RIN2 input RS-232 receiver 2 input. Accepts +/-15 V RS-232 line levels; typical input resistance 3-7 kohm.
5 DOUT1 output RS-232 driver 1 output. Swings to approximately +/-5 V (nominal) into a 3 kohm load; short-circuit current limited to ~60 mA.
6 DOUT2 output RS-232 driver 2 output. Swings to approximately +/-5 V (nominal) into a 3 kohm load; short-circuit current limited to ~60 mA.
7 NC unconnected Factory pin. May be left unconnected or tied to GND.
8 NC unconnected Factory pin. May be left unconnected or tied to GND.
9 DIN2 input CMOS-level driver 2 input, referenced to VL. Logic thresholds scale with VL (1.8, 3.3, or 5 V).
10 DIN1 input CMOS-level driver 1 input, referenced to VL. Logic thresholds scale with VL (1.8, 3.3, or 5 V).
11 ROUT2 output CMOS-level receiver 2 output; swings between 0 and VL. High-impedance when receivers are disabled by FORCEOFF.
12 ROUT1 output CMOS-level receiver 1 output; swings between 0 and VL. High-impedance when receivers are disabled by FORCEOFF.
13 INVALID output Invalid data output (active low). Asserts low when RIN inputs are between the +/-0.3 V to +/-2.4 V invalid thresholds or floating, signaling loss of an RS-232 partner. VL-referenced push-pull output.
14 FORCEOFF input Auto Powerdown control input (active low). When low, drivers and receivers are disabled and ROUT is Hi-Z; used with FORCEON to select normal, auto-powerdown, or shutdown mode. VL-referenced logic.
15 FORCEON input Auto Powerdown control input. Combined with FORCEOFF selects normal operation, Auto Powerdown Plus, or shutdown. VL-referenced logic.
16 C1- passive Negative terminal of the voltage-doubler charge-pump capacitor 1. Connect a 0.1 uF flying capacitor between C1+ and C1-.
17 GND power_in Device ground reference.
18 VL power_in Logic-level supply, 1.65 V to VCC. All CMOS inputs (DIN) and outputs (ROUT) are referenced to this rail, allowing direct interface with low-voltage MCUs/UARTs without an external level shifter. Bypass with a 0.1 uF capacitor to GND.
19 VCC power_in Charge-pump / device supply, 1.8 V, 3.3 V, or 5 V nominal (1.65 V to 5.5 V). Bypass with a 0.1 uF capacitor to GND.
20 V+ passive Positive charge-pump storage capacitor terminal. Connect a 0.1 uF capacitor between V+ and GND; V+ can reach up to +7 V in tripler mode.
21 C1+ passive Positive terminal of the voltage-doubler charge-pump capacitor 1. Pair with C1- via a 0.1 uF flying capacitor.
22 C2+ passive Positive terminal of the voltage-doubler charge-pump capacitor 2. Pair with C2- via a 0.1 uF flying capacitor.
23 C2- passive Negative terminal of the voltage-doubler charge-pump capacitor 2.
24 V- passive Negative charge-pump storage capacitor terminal. Connect a 0.1 uF capacitor between V- and GND; V- can reach down to -7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Interface
Pins 24

Ordering variants

Same part, different packaging or reel option.

  • TRS3122ERGER
  • TRS3122ERGERRGET

CAD (KiCad official)

  • Symbol: TRS3122ERGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
trs3122erger.step 277 KB You want the bare part, or you mark your own boards.
trs3122erger-etched.step 2.7 MB You want the part with TRS3122ERGER already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 663 faces against 158 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 a3329b69cad7abd6, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF